Uwe>> But all this needs substantial external logic, making the approach less
attractive.
As you point out - The true bottle neck is the USB transfer rate and the rate
the PC will actually poll for data - there are ways to improve this very simply
and cheaply
This device (FT2232H, or an FX2 chip)- coupled with a very small CPLD (or FPGA)
is the trick.
Pretty cheap: $60 - there are other variations - boards from Diligent are a
good example as are countless other Xilinx and Altera eval boards
http://www.knjn.com/FPGA-FX2.html <http://www.knjn.com/FPGA-FX2.html>
The Diligent Analog Discovery module is another good example
Dealing with the Data Rate
====================
the *DATA*RATE* solution It depends greatly on the logic signals you are
working with - and their actual rate of change and requires a little bit of
FPGA work
(This could also be done inside of a Cypres PSOC 5 - which is a small CortexM3
+ some digital/analog logic)
The theory is this:
Most of the time - Logic signals *DO*NOT* change
Or - you do not need all of those data bits
Or - there is a *LONG* pause when nothing is going on, followed by a
burst of activity when the transfer occurs, followed by another long pause
The problem is:
You need the sampling rate for the burst of activity
You pay the price in the long pause
Can you take advantage of this asymmetric data rate? I think you can.
Example #1
=========
You configure the the CPLD/FPGA to look for and collapse repeated values in a
run length encoded format.
For example - take the 8 bit data, and convert it to 16bits.
Byte 0 - is a time count (N sample clocks) that the signals have remained
steady.
Byte 1 - is the new sample data value at the end of (N) clocks
If the count over flows, you force output data- this is *SIMPLE* standard run
length encoding in hardware
This falls apart of course when the rate of change is to high - but that is
solvable - the FPGA could include some type of ‘status overflow’ bit the PC
driver could read at the end of the capture period, or - see Example #2
(If the guys from FTDI are listening … please add this feature to your chip!)
Example #2 - Raw Mode
=========
The FPGA could have side channel signals - say 3 bits - that act like a MODE
selection - From the FT2232 or FX2 that could disable this feature and make it
operate in a RAW mode “1 sample per 1 clock” Or perhaps make it operate in
*OTHER* modes - see Example #3
Or - you could get inventive … and reserve a few “time codes” - i.e.: 0xFF -
means the next 256 samples are *RAW* - not time collapsed - the solution then
becomes quite rate adaptive.
And - that high speed over head of 1/256 = is something that could be absorbed
by the FIFOs , or maybe bit (7:6) of the time code = 1 - the lower bits are a
count of RAW values that follow
Lots of ways of doing this
Example #3 - Other modes Nibbles
=========
Other examples are: You often do not require 8 bits - you need only 4 bits -
Examples are: I2C, SPI, CAN BUS, and UARTs - typically require 2 to 4 bits
This could - in other modes- bit pack samples into the high and low nibble of
the sample data - thus effectively cutting the data rate in half, or maybe
extending your REPEAT count to 12 bits
Often the FPGA can run at 2X or 3X or 10X the sample rate of the USB device -
what matters is the actual rate of change and how bursty your data actually is.
Again - it is important to have the error status bit that captures the overflow
condition - maybe it could also capture the sample number where the first error
occurred to better indicate where data went wrong.
FPGA vrs CPLD
============
An advantage of an FPGA solution - is they often contain a small bit of “RAM”
that can be used to extend/deepen the FX2/FT2232 FIFO memory
If you lay out your own board, or use an existing eval board (example: $149 -
from KNJN) - often Xilinx and Altera have example boards with an SDRAM/DDR
attached to the FPGA - huge external buffer
Input Voltage Selection
=================
This is something the KNJN FPGA boards do not support directly - they are I
believe always 3.3V IO (cheaper that way)
Another advantage of the CPLD/FPGA is this - they often have different IO
voltage banks :-)
Each group of pins has a separate VDD-IO signal and you can use different
voltages for each group of pins.
For example the FX2 and FT2232 - are 3.3V only parts - I deal with a lot of
1.8V parts - and I am seeing 1.2V parts - one or two small LDO’s (1.2 and 1.8V)
and a simple 3 position Jumper solves the voltage translation problem!
A fancier solution would be to use some of the IO pins to make some type of
voltage selector in software.
Again - if the guys from FTDI chip are listening - please support “VDD-IO” in
the rate of 1.0 to 3.3V this would be very helpful - requiring level shifters
is painful
Other Usages:
============
While the FT2232 - *can* - support JTAG - there are places where an FPGA can
really make things work much better - and very fast. For example many ARM
chips support something called “SWD” - a fundamental problem with SWD and
through put is the “busy” or “wait” response. The PC sends a command to the
target - the target then responds with a wait - this means the PC has to do a
“round trip” over USB to determine if it can proceed with the next transaction
or not. Yes, USB is fast if you are streaming lots of bytes - but it falls
apart when you are sending 8 bytes, waiting for a reply to check for busy, then
sending 8 bytes … in a ping pong fashion. Putting a little bit of logic into
the FPGA to handle the wait/retries would speed this up.
FPGA - For Xilinx - those little Red Boxes to program your FPGA
=====================
Xilinx is creating (releasing publicly) what is called the “Xilinx Virtual
Cable Driver” - it lets you create your own FPGA programer box
https://github.com/Xilinx/XilinxVirtualCable
<https://github.com/Xilinx/XilinxVirtualCable>
Not sure if Altera is going to follow suit - I think it would be great if they
did.
Result - and the point is this:
=====================
You can use the device to debug your software
Reconfigure (download FPGA image) use the same device to capture signals to
debug other things
If you have two (they are cheap, or you borrow your coworkers) - you can do
both at the same time.
A little software - and this little box I’m talking about is golden, it is a
swiss army knife
-Duane.
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