Hi!

I noticed that there has been no comments on this patch. Just let
me know if you would like to have some more explanation of the
problem, or in general, if you would like me to do anything in order
to ease the integration of this patch!

Best Regards,
Stefan

On Wed, Nov 11, 2015 at 04:46:51PM +0100, Stefan Ekenberg wrote:
> Fixes the problem that find_clk_edge() mistakenly detects a clock edge
> on the very first sampled value in case SPI mode 1 is used and the
> first sampled clock value i 0. This happens because oldclk is
> initialized to 1 and a clock sample of 0 will then mistakenly trigger a
> 1->0 transition (falling edge). Problem is solved by initializing
> oldclk with the first sampled value.
> ---
>  decoders/spi/pd.py |    6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py
> index 4a686dd..f87744c 100644
> --- a/decoders/spi/pd.py
> +++ b/decoders/spi/pd.py
> @@ -118,7 +118,7 @@ class Decoder(srd.Decoder):
>  
>      def __init__(self):
>          self.samplerate = None
> -        self.oldclk = 1
> +        self.oldclk = -1
>          self.bitcount = 0
>          self.misodata = self.mosidata = 0
>          self.misobits = []
> @@ -260,6 +260,10 @@ class Decoder(srd.Decoder):
>          if self.have_cs and not self.cs_asserted(cs):
>              return
>  
> +        # Initialize oldclk when the first sample is processed
> +        if self.oldclk == -1:
> +            self.oldclk = clk;
> +
>          # Ignore sample if the clock pin hasn't changed.
>          if clk == self.oldclk:
>              return
> -- 
> 1.7.10.4
> 

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