I would like to submit my new decoder for Renesas/Hitachi AUD (Advanced User Debugger) traffic. It decodes "Branch Trace" output (destination address for every branch/jump/call). There is a second mode "RAM monitor mode" that I haven't implemented as it is of less interest.
I also include one artificially-generated .sr dump of sample traffic; I would like to include the verilog file used to generate that dump but I read some guidelines that said ".sr only", so... I release the .sr dump to the public domain; the PD is GPLv3. I didn't attach the files in this email, I wasn't sure if the mailing list allows this ? I did a temp fork on github with the example dumps: https://github.com/fenugrec/sigrokdumps-tmp and a simple repo (not a fork) for the PD: https://github.com/fenugrec/sigrok-pd ------------------------------------------------------------------------------ Transform Data into Opportunity. Accelerate data analysis in your applications with Intel Data Analytics Acceleration Library. Click to learn more. http://pubads.g.doubleclick.net/gampad/clk?id=278785111&iu=/4140 _______________________________________________ sigrok-devel mailing list sigrok-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/sigrok-devel
