Tested this with my DSLogic Pro and can confirm that the device is now
initialized correctly enough for pulseview to correctly identify it
(when using the correct firmware from DreamSourceLabs).
On Thu, Mar 31, 2016, at 09:51 AM, Diego Asanza wrote:
> Hi,
>
> I got my dslogic to perform signal acquisition, but stills seems buggy.
>
> There were two main issues:
>
> 1. The fpga firmware upload in small chunks does not work. When done
> with only one call
> to libusb_bulk_transfer works fine.
>
> 2. The fpga configuration structure dslogic_fpga_config was not being
> correctly initialized.
> I just copied the initialization values from the original dslogic
> software.
>
> Regards,
> Diego.
>
> >From 5232341b5f60af2a3303a79eec9fe64870218af5 Mon Sep 17 00:00:00 2001
> From: "Diego F. Asanza" <f.asa...@gmail.com>
> Date: Wed, 30 Mar 2016 19:04:54 +0200
> Subject: [PATCH] Fix DSLogic FPGA binary image upload and signal
> acquisition.
>
> For some reason, uploading the fpga binary into dslogic in small chunks
> does
> not work. In this commit, the whole binary image is loaded into memory
> and
> transfer is done in one chunk.
>
> Furthermore, the fpga configuration structure was not initialized
> properly.
> This was changed with the initialization values taken from the original
> DSLogic software.
>
> Signed-off-by: Diego Asanza <f.asa...@gmail.com>
> ---
> src/hardware/fx2lafw/dslogic.c | 2 +-
> src/hardware/fx2lafw/dslogic.h | 19 ++++++++++++++-----
> 2 files changed, 15 insertions(+), 6 deletions(-)
>
> diff --git a/src/hardware/fx2lafw/dslogic.c
> b/src/hardware/fx2lafw/dslogic.c
> index ec8d534..9a3504f 100644
> --- a/src/hardware/fx2lafw/dslogic.c
> +++ b/src/hardware/fx2lafw/dslogic.c
> @@ -25,7 +25,7 @@
> #include "protocol.h"
> #include "dslogic.h"
>
> -#define FW_BUFSIZE (4 * 1024)
> +#define FW_BUFSIZE (1024 * 1024)
>
> #define FPGA_UPLOAD_DELAY (10 * 1000)
>
> diff --git a/src/hardware/fx2lafw/dslogic.h
> b/src/hardware/fx2lafw/dslogic.h
> index 5406769..17a6413 100644
> --- a/src/hardware/fx2lafw/dslogic.h
> +++ b/src/hardware/fx2lafw/dslogic.h
> @@ -64,8 +64,8 @@ struct dslogic_trigger_pos {
> */
> #define _DS_CFG(variable, wordcnt) ((variable << 8) | wordcnt)
> #define _DS_CFG_PAD(variable, wordcnt) ((_DS_CFG(variable, wordcnt)
> << 16) | 0xffff)
> -#define DS_CFG_START 0xffffffff
> -#define DS_CFG_MODE _DS_CFG(0, 1)
> +#define DS_CFG_START 0xf5a5f5a5
> +#define DS_CFG_MODE _DS_CFG(0, 1)
> #define DS_CFG_DIVIDER _DS_CFG_PAD(1, 2)
> #define DS_CFG_COUNT _DS_CFG_PAD(3, 2)
> #define DS_CFG_TRIG_POS _DS_CFG_PAD(5, 2)
> @@ -82,44 +82,53 @@ struct dslogic_trigger_pos {
> #define DS_CFG_TRIG_COUNT1 _DS_CFG_PAD(29, 16)
> #define DS_CFG_TRIG_LOGIC0 _DS_CFG_PAD(32, 16)
> #define DS_CFG_TRIG_LOGIC1 _DS_CFG_PAD(33, 16)
> -#define DS_CFG_END 0x00000000
> +#define DS_CFG_END 0xfa5afa5a
>
> struct dslogic_fpga_config {
> uint32_t sync;
> uint16_t mode_header;
> uint16_t mode;
> +
> uint32_t divider_header;
> uint32_t divider;
> uint32_t count_header;
> uint32_t count;
> +
> uint32_t trig_pos_header;
> uint32_t trig_pos;
> uint16_t trig_glb_header;
> uint16_t trig_glb;
> +
> uint32_t trig_adp_header;
> uint32_t trig_adp;
> uint32_t trig_sda_header;
> uint32_t trig_sda;
> +
> uint32_t trig_mask0_header;
> uint16_t trig_mask0[DS_NUM_TRIGGER_STAGES];
> uint32_t trig_mask1_header;
> uint16_t trig_mask1[DS_NUM_TRIGGER_STAGES];
> +
> uint32_t trig_value0_header;
> uint16_t trig_value0[DS_NUM_TRIGGER_STAGES];
> uint32_t trig_value1_header;
> uint16_t trig_value1[DS_NUM_TRIGGER_STAGES];
> +
> uint32_t trig_edge0_header;
> uint16_t trig_edge0[DS_NUM_TRIGGER_STAGES];
> uint32_t trig_edge1_header;
> uint16_t trig_edge1[DS_NUM_TRIGGER_STAGES];
> +
> uint32_t trig_count0_header;
> - uint16_t trig_count0[DS_NUM_TRIGGER_STAGES];
> + uint32_t trig_count0[DS_NUM_TRIGGER_STAGES];
> uint32_t trig_count1_header;
> - uint16_t trig_count1[DS_NUM_TRIGGER_STAGES];
> + uint32_t trig_count1[DS_NUM_TRIGGER_STAGES];
> +
> uint32_t trig_logic0_header;
> uint16_t trig_logic0[DS_NUM_TRIGGER_STAGES];
> uint32_t trig_logic1_header;
> uint16_t trig_logic1[DS_NUM_TRIGGER_STAGES];
> +
> uint32_t end_sync;
> };
>
> --
> 2.5.0
>
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