Hi Uwe & other sigrok maintainers,

Sorry to pester, I just wanted to check on this patch to restore DSLogic 
functionality.

Happy to make any changes necessary for it to be acceptable.


Angus

On Wed, Apr 12, 2017 at 05:38:14PM +1000, Angus Gratton wrote:
> Hi Mark,
> 
> Thanks for posting about this! I probably would have assumed my DSLogic was
> faulty and thrown it out (admittedly, I'm not much of a fan of it so I'm kind 
> of
> waiting for an excuse to replace it...)
> 
> I ran git bisect on libsigrok, and this was a regression in commit 8399f68a3:
> "fx2lafw: Use wide_sampling only if necessary". A workaround is to enable one 
> of
> the high 8 channels (9-15). This limits the maximum sample rate to 100MHz, and
> the maximum sample depth to 2MS (I think).
> 
> Possible patch is attached that fixes the problem by adding a device 
> capability
> for devices running the DSLogic firmware, rather than fx2lafw.
> 
> Cheers,
> 
> 
> Angus
> 
> On Mon, Apr 10, 2017 at 10:21:01AM -0700, Mark Haun wrote:
> > I just got an ebay DSLogic Pro working in sigrok Pulseview using the
> > information on the wiki.  I'm on Windows 7, using a nightly build from about
> > a week ago (0.4.0-git-8b9056d).
> > 
> > I'm seeing some strange behavior which could be a hardware issue, but feels
> > to me more like software or firmware.  When I look at a signal (on any
> > channel), the trace is low when the signal is low, but it toggles at Nyquist
> > when the signal is high.  That is, for any sample rate Fs chosen from the
> > dropdown menu, during high periods, the recorded trace is a square wave at
> > Fs/2.
> > 
> > I am using the threshold setting for 3.3v logic, which matches the device
> > under test.  (If I select the threshold for 5v logic, the traces are
> > constant low, as expected.)  Also, I've debugged the same circuit with a
> > Salae so I know it's working properly.
> > 
> > Has anyone seen this before?  Should I try the DSLogic version of sigrok
> > instead?
> > 
> > Mark
> > 
> > ------------------------------------------------------------------------------
> > Check out the vibrant tech community on one of the world's most
> > engaging tech sites, Slashdot.org! http://sdm.link/slashdot
> > _______________________________________________
> > sigrok-devel mailing list
> > sigrok-devel@lists.sourceforge.net
> > https://lists.sourceforge.net/lists/listinfo/sigrok-devel

> >From f8de8fdf82a06c3357efac5e87cad66622ecd315 Mon Sep 17 00:00:00 2001
> From: Angus Gratton <g...@projectgus.com>
> Date: Wed, 12 Apr 2017 17:26:45 +1000
> Subject: [PATCH] fx2lafw: Always enable wide sampling for dslogic firmware
> 
> Fixes regression in 8399f68a3.
> 
> Ref: https://sourceforge.net/p/sigrok/mailman/message/35780588/
> 
> Signed-off-by: Angus Gratton <g...@projectgus.com>
> ---
>  src/hardware/fx2lafw/api.c      | 21 ++++++++++++---------
>  src/hardware/fx2lafw/protocol.h |  2 ++
>  2 files changed, 14 insertions(+), 9 deletions(-)
> 
> diff --git a/src/hardware/fx2lafw/api.c b/src/hardware/fx2lafw/api.c
> index 1ad9bedc..e539e782 100644
> --- a/src/hardware/fx2lafw/api.c
> +++ b/src/hardware/fx2lafw/api.c
> @@ -57,29 +57,29 @@ static const struct fx2lafw_profile supported_fx2[] = {
>       /* DreamSourceLab DSLogic (before FW upload) */
>       { 0x2a0e, 0x0001, "DreamSourceLab", "DSLogic", NULL,
>               "dreamsourcelab-dslogic-fx2.fw",
> -             DEV_CAPS_16BIT, NULL, NULL},
> +             DEV_CAPS_16BIT | DEV_CAPS_DSLOGIC_FW, NULL, NULL},
>       /* DreamSourceLab DSLogic (after FW upload) */
>       { 0x2a0e, 0x0001, "DreamSourceLab", "DSLogic", NULL,
>               "dreamsourcelab-dslogic-fx2.fw",
> -             DEV_CAPS_16BIT, "DreamSourceLab", "DSLogic"},
> +             DEV_CAPS_16BIT | DEV_CAPS_DSLOGIC_FW, "DreamSourceLab", 
> "DSLogic"},
>  
>       /* DreamSourceLab DSCope (before FW upload) */
>       { 0x2a0e, 0x0002, "DreamSourceLab", "DSCope", NULL,
>               "dreamsourcelab-dscope-fx2.fw",
> -             DEV_CAPS_16BIT, NULL, NULL},
> +             DEV_CAPS_16BIT | DEV_CAPS_DSLOGIC_FW, NULL, NULL},
>       /* DreamSourceLab DSCope (after FW upload) */
>       { 0x2a0e, 0x0002, "DreamSourceLab", "DSCope", NULL,
>               "dreamsourcelab-dscope-fx2.fw",
> -             DEV_CAPS_16BIT, "DreamSourceLab", "DSCope"},
> +             DEV_CAPS_16BIT | DEV_CAPS_DSLOGIC_FW, "DreamSourceLab", 
> "DSCope"},
>  
>       /* DreamSourceLab DSLogic Pro (before FW upload) */
>       { 0x2a0e, 0x0003, "DreamSourceLab", "DSLogic Pro", NULL,
>               "dreamsourcelab-dslogic-pro-fx2.fw",
> -             DEV_CAPS_16BIT, NULL, NULL},
> +             DEV_CAPS_16BIT | DEV_CAPS_DSLOGIC_FW, NULL, NULL},
>       /* DreamSourceLab DSLogic Pro (after FW upload) */
>       { 0x2a0e, 0x0003, "DreamSourceLab", "DSLogic Pro", NULL,
>               "dreamsourcelab-dslogic-pro-fx2.fw",
> -             DEV_CAPS_16BIT, "DreamSourceLab", "DSLogic"},
> +             DEV_CAPS_16BIT | DEV_CAPS_DSLOGIC_FW, "DreamSourceLab", 
> "DSLogic"},
>  
>       /*
>        * Saleae Logic
> @@ -1004,10 +1004,13 @@ static int configure_channels(const struct 
> sr_dev_inst *sdi)
>       }
>  
>       /*
> -      * Use wide sampling if either any of the LA channels 8..15 is enabled
> -      * and/or at least one analog channel is enabled.
> +      * Use wide sampling if either any of the LA channels 8..15 is enabled,
> +      * or at least one analog channel is enabled,
> +      * or device is running DSLogic firmware not fx2lafw.
>        */
> -     devc->sample_wide = (channel_mask > 0xff || num_analog > 0);
> +     devc->sample_wide = (channel_mask > 0xff
> +                                              || num_analog > 0
> +                                              || (devc->profile->dev_caps & 
> DEV_CAPS_DSLOGIC_FW));
>  
>       return SR_OK;
>  }
> diff --git a/src/hardware/fx2lafw/protocol.h b/src/hardware/fx2lafw/protocol.h
> index e228c875..6260b3c5 100644
> --- a/src/hardware/fx2lafw/protocol.h
> +++ b/src/hardware/fx2lafw/protocol.h
> @@ -51,9 +51,11 @@
>  
>  #define DEV_CAPS_16BIT_POS   0
>  #define DEV_CAPS_AX_ANALOG_POS       1
> +#define DEV_CAPS_DSLOGIC_FW_POS 2
>  
>  #define DEV_CAPS_16BIT               (1 << DEV_CAPS_16BIT_POS)
>  #define DEV_CAPS_AX_ANALOG   (1 << DEV_CAPS_AX_ANALOG_POS)
> +#define DEV_CAPS_DSLOGIC_FW (1 << DEV_CAPS_DSLOGIC_FW_POS)
>  
>  #define DSLOGIC_FPGA_FIRMWARE_5V "dreamsourcelab-dslogic-fpga-5v.fw"
>  #define DSLOGIC_FPGA_FIRMWARE_3V3 "dreamsourcelab-dslogic-fpga-3v3.fw"
> -- 
> 2.12.2
> 

> ------------------------------------------------------------------------------
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