i'm thinking that the SUMP protocol could possibly be extended to
support analog channels.
that may see more use as a hybrid LA, Oscilloscope device
just that i'm not too sure if that may lead to some confusion 'out
there' with the different protocol features.
e.g. it could possibly be SUMP v2 perhaps
On 06/04/2018 09:49 AM, andrew goh via sigrok-devel wrote:
hi Ian,
I'm on an open sourced forum stm32duino, over there a forum member has
contributed a SUMP based implementation
http://www.stm32duino.com/viewtopic.php?t=1973&start=10#p27238
https://github.com/ddrown/stm32-sump
a google search turns up another one here
https://github.com/jpbarraca/LogicAlNucleo
On 06/04/2018 04:13 AM, Ian wrote:
I'm working on stm32f103 now and find the timer structure unhelpful
for logic analyzer use. Would be interested to see what you're doing.
Anything open source?
The various peripherals with DMA make a bus pirate like tool based on
the chip really complicated. For example nack/ack of i2c reads is
impossible in cli type interface. That's off topic though, sorry all.
Cheers,
Ian
Sent from a mobile device, please excuse my brevity.
On Jun 4, 2018, at 03:55, andrew goh <gohand...@yahoo.com
<mailto:gohand...@yahoo.com>> wrote:
Thanks Ian,
i noted that even with Hydrabus, it is really using the SUMP
protocol for the LA part that interfaces with sigrok.
As sigrok is pretty new to me, i'm not too sure if there are
other protocols which pretty much covers both analog and digital
channels.
one of those firmware like fx2lafw and the host/client side
libsigrok seem to such functionality but i've not delve into it
much yet.
The attractive part about stm32 devices isn't so much that they
are 'advanced', but they have quite a number of peripherals built
into the SOC.
e.g. for stm32f103 the 'lower end' of the series, it has
http://www.st.com/en/microcontrollers/stm32f103cb.html
2 x 12 bits adc (1 msps each, can be interleaved to do 2 msps,
multiple of channels, for less samp per sec). but 12 bits is a
good thing
Then it has on the soc dma (which allows better utilization of io
bandwidth, doing loops on a 72mhz mcu in flash ram won't be very
fast, dma relieves various bottlenecks).
it has several (2) sets of SPI, UART, I2C as peripherals.
USB 2.0 full speed is a built-in pheripheral in the soc
a rtc(real time clock) on soc
and the most of the various ports can be configured as gpios as a
'lowest common denominator'. the gpios hooked up to dma would
work pretty much as a digital signal recorder - logic analyzer,
storing the samples in sram on chip (but stm32f103cb has only got
20k)
because of the multitude of peripherals, an stm32 could work as a
multi-function device e.g. as both a LA or/and oscilloscope (not
necessarily concurrently, the higher end series probably can do
just that, lower end ones may run short of dma channels/streams).
the SPI, UART, I2C peripherals could in turn funnel data via USB
to the host, this works much like the FTDI usb-serial / other
protocol dongles. e.g. the hardware handles SPI, that becomes
simply 2 stream of data - MOSI and MISO and say if the SPI is
hooked up to a LCD display (another controller/mcu), these bytes
could be funneled back to sigrok. And sigrok would play a role
more like a protocol analyzer e.g. displaying what commands are
send to the lcd and what comes back.
While in general the firmware would normally run on the mcu. i'd
imagine that we could have the firmware run in an emulator on the
desktop the data gets funneled between the emulator - via sigrok
(middleman) - via usb - sigrok firmware on mcu - LCD. this makes
it a 'protocol analyzer' in that sense.
the LCD commands and responses gets displayed in sigrok. this is
pretty round about but it may literally be useful in situations
e.g. when debugging firmware in the emulator on the pc.
Cheers,
Andrew
On 06/04/2018 02:49 AM, Ian wrote:
I have a bus pirate about to release with 16 million samples per
channel LA with a theoretical 100msps speed (but we'll be around
72msps). I'd be interested in doing whatever to get updated
support into the release as I'm developing a uni level text book
that would make use of sigrok.
The SUMP protocol is really insufficient for this, the sample
counter only goes to 0xFFFF so only a fraction of the sample
space is available.
Please let me know if advance hardware would be helpful.
Cheers,
Ian, in Shenzhen, China
Sent from a mobile device, please excuse my brevity.
On Jun 4, 2018, at 00:39, andrew goh via sigrok-devel <
sigrok-devel@lists.sourceforge.net
<mailto:sigrok-devel@lists.sourceforge.net>> wrote:
Thanks Aleksander!
found some links:
https://hydrabus.com/hydrabus-1-0-specifications/
https://github.com/hydrabus/hydrabus
https://github.com/hydrabus/hydrafw
Hydrabus Board is actually based on stm32
On 06/04/2018 12:14 AM, Aleksander Alekseev wrote:
Hello Andrew,
Take a look on HydraBus project and corresponding firmware,
HydraFW. If I'm not mistaken it claims to be compatible
with BusPirate protocol. However last time I checked
BusPirate support in Sigrok was broken. Check the bug tracker.
As a side note assembled HydraBus is overpriced, better
order PCB on JLCPCB and solder it manualy. Or try to run
HydraFW on some development board from eBay.
Sorry I'm in an airport right now thus I can't give direct
links.
On Sun., 3 Jun. 2018, 17:32 andrew goh via sigrok-devel, <
sigrok-devel@lists.sourceforge.net
<mailto:sigrok-devel@lists.sourceforge.net>> wrote:
hi all,
i'm a newbie, novice to sigrok, just hope to get some
pointers.
there are many stm32 based development boards (e.g. the
discovery and
nucleo series from ST itself), and there are many
others which can be
purchased on ebay etc for a rather low cost. e.g. if
one search for
stm32f103 on ebay one could come across boards like
blue pill or maple
mini that goes as low as $2. these devices based on arm
cortex-m3 runs
at 72mhz has 2 adc which could push an envelop of about
2msps sampling
speeds and gpios in the 10s of mhz. then the higher end
devices e.g. m4
stm32f407 runs at 168mhz has adcs that run up to 7msps
and gpio sampling
speeds faster than the m3 series and the larger ve-zg
devices has decent
amount of ram e.g. 64k-192k sram. and stm32 f3 series
has adc that can
push 18msps quad interleaved. hence despite a only an
on chip-full
speed usb 2.0, they can work as oscilloscopes or logic
analyzers by
storing the adc samples to ram and later transmit that
over usb. it
won't be those 100msps speeds but may be still useful
for the lower mhz
analysis
if i want to turn these boards to interface with sigrok
/ pulseview etc.
where do i start looking for info?
are there any 'standard' sigrok protocols for
oscilloscopes and logic
analyzers where i can just build the firmware on the
stm32 soc so that
they'd 'just work' without changes at sigrok end?
thanks in advance.
andrew
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