Currently we are aiming for Sigrok support for the Kingst LA2016 (200MHz
sampling). The LA1016 uses the same hardware but is limited to 100MHz
sampling. It operates in the same way and it could be supported quite
easily once LA2016 support is in place. I had hoped that loading the
LA2016 bitstream onto the LA1016 would enable 200MHz operation, but no.
There is an authentication chip adjacent to the LED, SOIC8, call it
'KAuth'. When the FPGA boots up it receives 16 bytes from 'KAuth' to
authenticate the bitstream. So no easy upgrade. It seems that after
Kingst started out by copying Saleae products
(https://sigrok.org/wiki/KingST_KQS3506-LA16100) they learned to put
quite some effort into locking their own products.
I still believe that the FPGA bitstream needs to be extracted from USB
packets rather than software resource files on disk. But I hope I am
wrong, because that is cumbersome for PV users.
Anyway, I continue to experiment. It seems the EEPROM bytes that are
read when connecting to the LA (prior to bitstream load) are purchase
date and unit type (LA2016/LA1016/others). See updated Python code in
repo below. Method set_model_identity() if you are interested.
Regards,
On 2021-01-10 20:01, Kevin Grant wrote:
Hello,
Here is the python code I have been using for LA2016 experiments.
https://bitbucket.org/magellanic-clouds/klarty/src/master/
Included there is a text file with my thoughts on the PV code, see
notes-sigrok-pv-issues.txt
I used FX2 fw from KingstViz-linux v3.4.2 and FPGA bitstream extracted
from KingstViz-Win v3.4.3 USB packets.
Hardware version as printed on PCB: LA-2016 v1.3.0.
Regards
Kevin
_______________________________________________
sigrok-devel mailing list
sigrok-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/sigrok-devel
_______________________________________________
sigrok-devel mailing list
sigrok-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/sigrok-devel
