Thanks for the links, but based on information in those links it appears that in USB1.1 the Bulk Endpoints only support 64B transfers (you need USB 2.0 to reach 512). The rp2040 indicates 1023B for Isoch and 64B for all others but I could be misreading things...
I think I'm already getting 64B transfers with serial CDC because when I send >64B to the TUD interface I see the available bytes go down in groups of 64 bytes at a time. I have demonstrated sustained 600KB/sec (4.8Mbps) transfer rates using serial CDC. USB 1.1 will at best be 9.6Mbit/sec due to 8b/10b encoding, and likely much worse when you account for delays in switching between host/device etc. On Thu, Mar 17, 2022 at 12:41 PM <arnyt...@seznam.cz> wrote: > S. W. This is cool! I was looking at the USB TMC class: > https://www.tmatlantic.com/…919 > <https://www.tmatlantic.com/encyclopedia/index.php?ELEMENT_ID=13919> > > In theory it should be much faster than CDC class because it uses BULK > transfers insread of CONTROL transfers. Bulk transfers can have multiple > packets in the frame, > so threoretically it should use most of the USB 2.0 FS bandwith, which is > 12Mbit/s. > > https://www.keil.com/…tml > <https://www.keil.com/pack/doc/mw/USB/html/_u_s_b__bulk__transfers.html> > https://www.beyondlogic.org/…tml > <https://www.beyondlogic.org/usbnutshell/usb1.shtml> > > Markb139 used timers, which isnt bad, but I thing that using the PIO + DMA > combo is better because you are not depending as much on the CPU and the > PIO frequency is easily set. > I would like to remove buffering entirely, and use DMA to directly send > data to TinyUSB, (microphone example is using exactly that, and I think it > can work for the USB TMC class too), maybe use another PIO for compression > of some sort, leaving the CPU almost free. > > tabbey01 I am more into hardware than programming xd. The reason my driver > is complex is because it pack readed bits dynamically. With my tests, I got > someting more than 1Mbit/s so if you choose to > sample in 1MHz it will sample only one channel. This have the advantage > that you can choose if you want more pins with smaller sample speed or less > on higher frequency. Its pretty effitient with using the USB bandwidth. > > The pico is really powerful for its price and it would be really nice to > have an universal driver in sigrok (the SUMP is really bad, because you > cant stream the samples, it will show them in the reverse order). I think > it can be also a really good programmer/impedance > measurement/oscilloscope/gpio tool. > > > sorry for english :) > > A.T. > ---------- Původní e-mail ---------- > Od: Shawn Walker <ac0b...@gmail.com> > Komu: Tony Abbey <tabbe...@gmail.com> > Datum: 17. 3. 2022 14:57:19 > Předmět: Re: [sigrok-devel] New sigrok driver for homemade logic analyzer > > Looks like we've got a party :) > A.T. It looks like you have all the basic elements of a driver, and use > dma buffering which is cool. > > I submitted this pull request > https://github.com/sigrokproject/libsigrok/pull/181 for my version. > I added 3 analog channels and up to 21 logic channels as well as SW > triggering and run length encoding. > > There is also https://github.com/markb139/pico_logic with driver > https://github.com/markb139/libsigrok. markb139's implementation is > interesting because it uses a real USB TMC implementation rather than > serial CDC (I'm really interested to know if that provides noticeable > bandwidth improvements). At this point markb139 hasn't submitted an > official pull request, waiting at least in part to figure out USB ID issues. > > Note: I'm not a moderator/curator or approver for the sigrok repos, and I > have not had any contact from the developer as to which of any (or a merge > or ???) might be pulled into the official sigrok repo. > > Shawn > > > > > On Thu, Mar 17, 2022 at 3:04 AM Tony Abbey <tabbe...@gmail.com> wrote: > > Your code for the Pico looks interesting. I'm not sure how your proposed > patching of sigrok will work. It's all getting a bit complex for me as an > engineer rather than a programmer! > Tony > > > On Tue, 15 Mar 2022, 08:48 , <arnyt...@seznam.cz> wrote: > > Hello. > > I am student from Czech Republic and I am graduating this year. > For my graduation project, I choose to create logic analyzer with rp2040 > and your amazing open source program Sigrok. > I have the code in working state and had an idea, if would be possible to > contribute it, becase the compiling is not the easiest thing if others want > to make it too. > Patech are sent as attachments to this mail. The code is not ideal, i > think its not even with the guidelines ":) so I wont be sad if you wont add > it. > I want to say big thank you for the program you developing, open source > communities are amazing :D. > > project repo: https://github.com/…ool <https://github.com/arnytrty/iotool> > > Sincerently > A.T. > _______________________________________________ > sigrok-devel mailing list > sigrok-devel@lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/sigrok-devel > > _______________________________________________ > sigrok-devel mailing list > sigrok-devel@lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/sigrok-devel > >
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