Fix the field sequence for the I/O write and Memory write cycle types.
Previously the state machine was using the same sequence for read and
write cycles.
---
decoders/lpc/pd.py | 22 +++++++++++++++++-----
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/decoders/lpc/pd.py b/decoders/lpc/pd.py
index 8ab2faf..273420d 100644
--- a/decoders/lpc/pd.py
+++ b/decoders/lpc/pd.py
@@ -149,6 +149,7 @@ def reset(self):
self.cycle_type = -1
self.databyte = 0
self.tarcount = 0
+ self.write_dir = -1
self.synccount = 0
self.ss_block = self.es_block = None
@@ -180,6 +181,7 @@ def handle_get_ct_dr(self):
# LAD[3:0]: Cycle type / direction field (1 clock cycle).
self.cycle_type = fields['CT_DR'].get(self.lad, 'Reserved / unknown')
+ self.write_dir = (self.lad & 0b0010) >> 1 # LAD1 == 1
# TODO: Warning/error on invalid cycle types.
if 'Reserved' in self.cycle_type:
@@ -219,8 +221,12 @@ def handle_get_addr(self):
self.putb([3, [s % self.addr]])
self.ss_block = self.samplenum
- self.state = 'GET TAR'
- self.tar_count = 0
+ if self.write_dir:
+ self.cycle_count = 0
+ self.state = 'GET DATA'
+ else:
+ self.state = 'GET TAR'
+ self.tarcount = 0
def handle_get_tar(self):
# LAD[3:0]: First TAR (turn-around) field (2 clock cycles).
@@ -261,8 +267,11 @@ def handle_get_sync(self):
# TODO
- self.cycle_count = 0
- self.state = 'GET DATA'
+ if self.write_dir:
+ self.state = 'GET TAR2'
+ else:
+ self.cycle_count = 0
+ self.state = 'GET DATA'
def handle_get_data(self):
# LAD[3:0]: DATA field (2 clock cycles).
@@ -284,7 +293,10 @@ def handle_get_data(self):
self.ss_block = self.samplenum
self.cycle_count = 0
- self.state = 'GET TAR2'
+ if self.write_dir:
+ self.state = 'GET TAR'
+ else:
+ self.state = 'GET TAR2'
def handle_get_tar2(self):
# LAD[3:0]: Second TAR field (2 clock cycles).
--
2.30.2
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