Hello, I was recently discussing the logic analyzers capabilities (Which logic analyzer for FPGA work up to 300-400 Mhz - https://www.eevblog.com/forum/testgear/which-logic-analyzer-for-fpga-work-up-to-300-400-mhz/ ). A question appeared if sigrok can be used in the following scenario:
Consider a system with a 100MHz clock, an address bus, a data bus, and an address valid signal. Every 1ms data is read, and you are only interested in reads from address in the range 1234 to 5678. You want to capture (up to) 10000 values read on the rising edge of the clock provided address valid is asserted and provided the address range is right. Would be possible to clarify if sigrok can be used in such case ? Thanks. Dimitar _______________________________________________ sigrok-devel mailing list sigrok-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/sigrok-devel
