You are using a CMP.L2Shared simulator so your L2 will be shared. Regards, -Stavros
On Jun 24, 2010, at 12:07 PM, mihai pricopi wrote: By setting the number of L2 cores the number of L1 caches (instr+data) would that still mean that the L2 cache is fully shared by cores ? On Thu, Jun 24, 2010 at 6:03 PM, Volos Stavros <[email protected]<mailto:[email protected]>> wrote: Dear Mihai, It's good to "reply all" so someone can follow the mails in case he has the same problem with you. Briefly: net-mapper:Cores should be the number of cores of your cmp (in your case: 4) L2:cores should be the number of L1 caches x 2 (L1-i and L1id) (in your case: 8) L1:cores this actually is the number of hardware threads running on L1 (in your case: 1 because you don't have multithreading) Regads, -Stavros On Jun 24, 2010, at 11:54 AM, mihai pricopi wrote: Hi, Thanks allot Stavros. I am a bit confused about the memory configurations in the timing scripts but I will try to see what exactly do they mean. At a glance I guess the Cores for the net-mapper must be set to 4. I shall see if I would have to do other modifications. flexus.set "-net-mapper:Cores" "4" # "Number of cores" (Cores) Thanks Mihai On Thu, Jun 24, 2010 at 5:42 PM, Volos Stavros <[email protected]<mailto:[email protected]>> wrote: Mihai, The timing_v9 configuration file assumes single core processors. You used a CMP simulator to create flexpoints for 4-core CMP and you are trying to run timing simulations of these flexpoints with a 4-core CMP timing simulator using the timing_v9. If you read carefully the instructions in the guide the examples are for creating flexpoints with a uniprocessor simulator and then run them with a uniprocessor OoO. If you try to follow the instructions of the guide you need to define UP.Trace for the flexpoints. You need to create your trace/timing configuration files for the simulator that you simulate. Regards, -Stavros On Jun 24, 2010, at 11:17 AM, mihai pricopi wrote: Ok, they are the default ones that come with the flexus4.0. But I attached then anyway. On Thu, Jun 24, 2010 at 5:11 PM, Volos Stavros <[email protected]<mailto:[email protected]>> wrote: Mihai, I need the configuration files that are located in the specs folder: trace and timing_v9 Regards, -Stavros On Jun 24, 2010, at 11:07 AM, mihai pricopi wrote: Ok, I attached the logs. On Thu, Jun 24, 2010 at 4:58 PM, mihai pricopi <[email protected]<mailto:[email protected]>> wrote: Ok Stavros, just a second. On Thu, Jun 24, 2010 at 4:54 PM, Volos Stavros <[email protected]<mailto:[email protected]>> wrote: Dear Mihai, 1) Phases are "independent" phases of your workload. For example if you have 2 phases (phase_000, phase_001) you create the simics checkpoints in these two different phases and then you can treat them as "independent" workloads in the sense that the generation of the flexpoints of the two phases can be done in the same time. 2) This means that the trace and timing configuration files that you are using are not compatible. Can you attach both of them so I can see what is wrong? Regards, -Stavros On Jun 24, 2010, at 10:38 AM, mihai pricopi wrote: Hi Stavros, Thanks for your information. I would have 2 more questions: 1) What is the use of phase and what does Flexus means by phases ? 2) I created 28 flexpoints of the test application using this command: "run_job -postprocess "/home/mihai/flexus-4.0/scripts/postprocess_ckptgen.sh flexpoint 28 test_app" -cfg trace -run flexpoint -local -ckpt-gen CMP.L2Shared.Trace flexus_test_app_v9" When i want to run the timing_simualtion with this command: "run_job -ma -cfg timing_v9 -run timing -local -state test_app CMP.L2SharedNUCA.OoO flexus_test_app_v9" I get this error: .................................................... 190 <ComponentManager.cpp:132> {0}- Done loading. 191 <WhiteBoxImpl.cpp:178> {4}- initializing idle_thread_t's, num procs=4 sys width=4 191 <WhiteBoxImpl.cpp:178> {4}- initializing idle_thread_t's, num procs=4 sys width=4 192 <WhiteBoxImpl.cpp:195> {4}- CPU[0] idle_thread_t point at paddr: p:000000000 192 <WhiteBoxImpl.cpp:195> {4}- CPU[0] idle_thread_t point at paddr: p:000000000 193 <WhiteBoxImpl.cpp:203> {4}- No CPU was able to translate the virtual address of the cpu struct for cpu 1 193 <WhiteBoxImpl.cpp:203> {4}- No CPU was able to translate the virtual address of the cpu struct for cpu 1 194 <mai_api.cpp:93> {4}- CPU[0] Registering for interrupts 194 <mai_api.cpp:93> {4}- CPU[0] Registering for interrupts 195 <mai_api.cpp:93> {4}- CPU[2] Registering for interrupts 195 <mai_api.cpp:93> {4}- CPU[2] Registering for interrupts 196 <mai_api.cpp:93> {5}- CPU[3] Registering for interrupts 196 <mai_api.cpp:93> {5}- CPU[3] Registering for interrupts 197 <ValueTracker.hpp:199> {6}- Registering DMA tracker 197 <ValueTracker.hpp:199> {6}- Registering DMA tracker 198 <ValueTracker.hpp:248> {6}- Connecting to DMA memory map 198 <ValueTracker.hpp:248> {6}- Connecting to DMA memory map 199 <ValueTracker.hpp:251> {6}- Done registering DMA tracker 199 <ValueTracker.hpp:251> {6}- Done registering DMA tracker 200 <mai_api.cpp:93> {7}- CPU[1] Registering for interrupts 200 <mai_api.cpp:93> {7}- CPU[1] Registering for interrupts 201 <component.hpp:269> {34}- <undefined> Assertion failed: ((!(anIndex < theWidth))) : Component: net-mapper Index: 3 Width: 1 Abort (SIGABRT) in main thread Crash stack trace: #0 0x00eb6422 <unknown> #1 0x0014d932 <unknown> #2 0x07223f67 <unknown> #3 0x07225635 <unknown> #4 0x0727f5b3 <unknown> #5 0x07229173 <unknown> #6 0x06c38ef1 <unknown> #7 0x06c39c29 <unknown> #8 0x06cea645 <unknown> #9 0x06cf7bb8 <unknown> #10 0x06c7c07e <unknown> #11 0x0733b1f2 <unknown> #12 0x0733b23f <unknown> #13 0x073ad592 <unknown> #14 0x073aca69 <unknown> #15 0x008d6309 <unknown> #16 0x008d6a7b <unknown> #17 0x008d6b68 <unknown> #18 0x0095ae06 <unknown> #19 0x0095b00f <unknown> #20 0x0095b219 <unknown> #21 0x00938e98 <unknown> #22 0x002b0ef2 <unknown> #23 0x002ebe1b <unknown> #24 0x002eb43d <unknown> #25 0x002ec690 <unknown> #26 0x0029fc2c <unknown> #27 0x00288040 <unknown> #28 0x002e493c <unknown> #29 0x002dd1e2 <unknown> #30 0x002b0ef2 <unknown> #31 0x002ebe1b <unknown> #32 0x002ec690 <unknown> #33 0x002ea588 <unknown> #34 0x002ec690 <unknown> #35 0x002ea588 <unknown> #36 0x002ec690 <unknown> #37 0x002ea588 <unknown> #38 0x002ec690 <unknown> #39 0x002ea588 <unknown> #40 0x002ec690 <unknown> #41 0x002ea588 <unknown> #42 0x002ec690 <unknown> #43 0x002ec837 <unknown> #44 0x00951698 <unknown> #45 0x008dcdc6 <unknown> #46 0x008dd160 <unknown> #47 0x008dd3f8 <unknown> #48 0x0804add3 <unknown> #49 0x00136b56 <unknown> #50 0x08049891 <unknown> The simulation state has been corrupted. Simulation cannot continue. Please restart Simics. .......................................... Do you have any idea what am I doing wrong ? Is complaining something about an index being smaller than the width. The width I suppose it should be 4 since my simulation has 4 cores. Thanks Mihai On Thu, Jun 24, 2010 at 4:27 PM, Volos Stavros <[email protected]<mailto:[email protected]>> wrote: Hi Mihai, This command is placed for running timing simulations. 0 means phase_000 1-10 means that flexpoints 1-10 are used in timing simulation Therefore flexpoints 1 to 10 of phase_000 will be executed. flexus_commands_timing(common) is placed in the beginning of the file and says how many cycles will be executed and how big the interval of each region is. We use 150000 cycles for each flexpoint and region interval 50000. The first 100000 is to warmup the microarchitectural components and the rest 50000 cycles are used for the timing simulation Regards, -Stavros On Jun 24, 2010, at 10:10 AM, mihai pricopi wrote: > Hi, > > In this line in .run_job.rc.tcl : > > "{ flexus_test_app_v9 baseline 0:1-10 > $flexus_commands_timing(common) }" > > What exactly 0:1-10 means ? > I`ve also seen that for other running configurations there is also something > like this: 0-10:5-24 > > Regards > <logs.tar.gz> <conf_files.tar.gz>
