Dear all Flexus people:
I love Flexus very much and I appreciate all of you.
However, I am afraid if Flexus does not model x86 so extensively as sparc v9
architecture.
Can I ask to what extent Flexus models x86 TLB?
For instance, x86 TBL must be flushed at every context switch which
indispensably updates CR3 register value.
(This is the biggest overhead with x86 context switch.)
Does Flexus reflect this effect when evaluating total memory subsystem
performance (latency)?
Thank you very much.
Best regards,
Suk chan Kang
