Hi Song, You can use the following patch to fix this bug. Please apply this patch and let me know whether you face any other bug/assertion.
Regards, -Stavros. On Apr 5, 2011, at 5:21 PM, Song Liu wrote: > Hi Volos, > > Thanks so much for this helpful information. > > After changing the number of banks, I have fixed most of the assertion > fails, with only one exception. Could you please help me look at the > attached assertion fail? > > Thanks again, > > Best, > Song > > > On Tue, Apr 5, 2011 at 3:42 AM, Volos Stavros <[email protected]> wrote: >> Hi Song, >> >> Please ignore the previous email. >> >> The problem is the number of L2 banks. You have set this parameter to 1 >> which is wrong. During the trace >> simulation the directory and cache state are NOT seperate for each bank, so >> we need to load the correct data >> to each bank from these files. Since you have set the number of banks to 1 >> (less than the number of tiles >> that you simulate) the loading of the state will not be correct and that's >> why you experience this problem. >> >> Please set the number of banks to the number of tiles (i.e., cores) you are >> simulating. According to the topology >> you are using, you are simulating 4 cores. So the correct value is >> >> -L2:banks 4 # (Banks) number of >> directory banks in each group >> >> Regads, >> -Stavros. >> >> ________________________________________ >> From: Song Liu [[email protected]] >> Sent: Tuesday, April 05, 2011 4:22 AM >> To: [email protected] >> Subject: Re: Error with flexus_test_app in multi-core system >> >> Hi Jason, >> >> Thanks for your kind reply. I have attached the two configuration.out files. >> >> Best, >> Song >> >> On Mon, Apr 4, 2011 at 8:45 PM, Jason Zebchuk <[email protected]> >> wrote: >>> Hi Song, >>> >>> The line >>> >>> 28276 <NonInclusiveMESIPolicy.cpp:375> {51794}- Received Upgrade from >>> Non-Sharer, converting to WriteReq: MemoryMessage[Upgrade Request]: >>> Addr:0xp:0003bdc80 Size:0 Serial: 9898 Core: 0 DStream: true Outstanding >>> Msgs: 0 Requires Ack >>> >>> Indicates that the coherence directory located with the L2 cache indicates >>> that the requester is not a sharer of the block. It uses this condition to >>> identify the race condition I mentioned in my previous email. However, if we >>> look at the other messages, we see that there is no race happening. So, >>> 00-L1d has a valid copy but this isn't recorded in the directory. >>> >>> So, either there's a bug in the code, or there's something in your >>> configuration that's making this happen. >>> >>> Can you reply to the list and send your configuration.out from your timing >>> simulation, and the configuration.out from the functional simulation that >>> created any flex-state that you might be loading? Can you please send them >>> as attachments instead of inline? >>> >>> >>> Thanks, >>> >>> Jason >>> >>> >>> >>> On 11-04-04 7:43 PM, Song Liu wrote: >>>> >>>> Hi Jason, >>>> >>>> Thanks a lot for your kind reply. >>>> >>>> I am not using different cache block sizes, so I guess that is not the >>>> reason. >>>> >>>> I have included all the debug information for the specific address in >>>> the following. >>>> >>>> Thanks again, >>>> >>>> Song >>>> >>>> 28123<CacheController.hpp:366> {51765}- Searching MAF for block >>>> p:0003bdc80 >>>> 28126<StdArray.hpp:584> {51765}- Found block p:0003bdc80 >>>> (p:0003bdc80) in set 114 in state Shared >>>> 28171<CacheController.hpp:366> {51773}- Searching MAF for block >>>> p:0003bdc80 >>>> 28174<StdArray.hpp:584> {51773}- Found block p:0003bdc80 >>>> (p:0003bdc80) in set 114 in state Shared >>>> 28207<CacheController.hpp:366> {51780}- Searching MAF for block >>>> p:0003bdc80 >>>> 28210<StdArray.hpp:584> {51780}- Found block p:0003bdc80 >>>> (p:0003bdc80) in set 114 in state Shared >>>> 28244<CacheController.hpp:366> {51788}- Searching MAF for block >>>> p:0003bdc80 >>>> 28247<StdArray.hpp:584> {51788}- Found block p:0003bdc80 >>>> (p:0003bdc80) in set 114 in state Shared >>>> 28253<CacheController.hpp:291> {51788}- 02-L1d - Adding MAF entry for >>>> block p:0003bdc80 in state kWaitResponse >>>> 28255<CacheController.cpp:1846> {51789}- 02-L1d sendBack_Request >>>> MemoryMessage[Upgrade Request]: Addr:0xp:0003bdc80 Size:0 Serial: 9898 >>>> Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28257<CacheImpl.cpp:454> {51789}- 02-L1d Sent on Port >>>> BackSideOut(Request): MemoryMessage[Upgrade Request]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9898 Core: 0 DStream: true >>>> Outstanding Msgs: 0 Requires Ack >>>> 28258<SplitDestinationMapperImpl.cpp:813> {51789}- sys-net-mapper >>>> Dest = 6 (dirIndex2NodeIndex(2)):MemoryMessage[Upgrade Request]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9898 Core: 0 DStream: true >>>> Outstanding Msgs: 0 Requires Ack >>>> 28259<SplitDestinationMapperImpl.cpp:346> {51789}- sys-net-mapper >>>> Received Request from cache 2 sending to network port 8 - >>>> MemoryMessage[Upgrade Request]: Addr:0xp:0003bdc80 Size:0 Serial: 9898 >>>> Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28261<MultiNicXImpl.hpp:210> {51790}- 02-nic Packet contains: >>>> MemoryMessage[Upgrade Request]: Addr:0xp:0003bdc80 Size:0 Serial: 9898 >>>> Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28263<MemoryNetworkImpl.cpp:306> {51790}- Network Received msg From 2 >>>> to 6, on vc 0, serial: 2036 Message = MemoryMessage[Upgrade Request]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9898 Core: 0 DStream: true >>>> Outstanding Msgs: 0 Requires Ack >>>> 28265<MemoryNetworkImpl.cpp:190> {51793}- Network Delivering msg From >>>> 2 to 6, on vc 2, serial: 2036 Message = MemoryMessage[Upgrade >>>> Request]: Addr:0xp:0003bdc80 Size:0 Serial: 9898 Core: 0 DStream: true >>>> Outstanding Msgs: 0 Requires Ack >>>> 28267<MultiNicXImpl.hpp:138> {51793}- 06-nic Packet contains: >>>> MemoryMessage[Upgrade Request]: Addr:0xp:0003bdc80 Size:0 Serial: 9898 >>>> Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28268<SplitDestinationMapperImpl.cpp:642> {51794}- sys-net-mapper >>>> Received Request for Directory 2 - MemoryMessage[Upgrade Request]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9898 Core: 0 DStream: true >>>> Outstanding Msgs: 0 Requires Ack >>>> 28269<CMPCacheImpl.cpp:140> {51794}- 02-L2 Received on Port >>>> Request_In : MemoryMessage[Upgrade Request]: Addr:0xp:0003bdc80 Size:0 >>>> Serial: 9898 Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> from node 4 >>>> 28270<CMPCacheController.hpp:124> {51794}- 02-L2reserveSnoopOut(2): >>>> ProcRequest: NoAction, snoop reservations: 0, request reservations: 0, >>>> reply reservations: 0, MemoryMessage[Upgrade Request]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9898 Core: 0 DStream: true >>>> Outstanding Msgs: 0 Requires Ack >>>> 28272<CMPCacheController.cpp:345> {51794}- 02-L2 Scheduled Request: >>>> MemoryMessage[Upgrade Request]: Addr:0xp:0003bdc80 Size:0 Serial: 9898 >>>> Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28273<CMPCacheController.cpp:438> {51794}- 02-L2 handleRequest: >>>> ProcRequest: NoAction, snoop reservations: 2, request reservations: 1, >>>> reply reservations: 1, MAF reserved, Cache EB reserved (1), Dir EB >>>> reserved, MemoryMessage[Upgrade Request]: Addr:0xp:0003bdc80 Size:0 >>>> Serial: 9898 Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> for MemoryMessage[Upgrade Request]: Addr:0xp:0003bdc80 Size:0 Serial: >>>> 9898 Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28274<StdArray.hpp:566> {51794}- Looking for block p:0003bdc80 in set >>>> 3954 theNumSets = 8192 >>>> 28275<StdArray.hpp:568> {51794}- Found block p:0003bdc80 in set 3954 >>>> in state Exclusive >>>> 28276<NonInclusiveMESIPolicy.cpp:375> {51794}- Received Upgrade from >>>> Non-Sharer, converting to WriteReq: MemoryMessage[Upgrade Request]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9898 Core: 0 DStream: true >>>> Outstanding Msgs: 0 Requires Ack >>>> 28277<CMPCacheController.hpp:156> {51794}- 02-L2unreserveSnoopOut(1): >>>> ProcRequest: NotifyAndWaitAck, snoop reservations: 2, request >>>> reservations: 1, reply reservations: 1, MAF reserved, Cache EB >>>> reserved (1), Dir EB reserved, MemoryMessage[Write Request]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9898 Core: 0 DStream: true >>>> Outstanding Msgs: 0 Requires Ack >>>> 28279<CMPCacheController.cpp:523> {51794}- 02-L2 runRequestProcess: >>>> ProcRequest: NotifyAndWaitAck, snoop reservations: 1, request >>>> reservations: 0, reply reservations: 1, MemoryMessage[Write Request]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9898 Core: 0 DStream: true >>>> Outstanding Msgs: 0 Requires Ack for MemoryMessage[Write Request]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9898 Core: 0 DStream: true >>>> Outstanding Msgs: 0 Requires Ack >>>> 28280<CMPCacheController.cpp:757> {51798}- Finalize process: >>>> ProcRequest: NotifyAndWaitAck, snoop reservations: 1, request >>>> reservations: 0, reply reservations: 1, MemoryMessage[Write Request]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9898 Core: 0 DStream: true >>>> Outstanding Msgs: 0 Requires Ack >>>> 28281<CMPCacheController.hpp:156> {51798}- 02-L2unreserveSnoopOut(1): >>>> ProcRequest: NotifyAndWaitAck, snoop reservations: 1, request >>>> reservations: 0, reply reservations: 1, MemoryMessage[Write Request]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9898 Core: 0 DStream: true >>>> Outstanding Msgs: 0 Requires Ack >>>> 28283<CMPCacheController.cpp:844> {51798}- 02-L2 enqueuing Snoop msg: >>>> MemoryMessage[WriteFwd]: Addr:0xp:0003bdc80 Size:0 Serial: 9899 Core: >>>> 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28285<CMPCacheImpl.cpp:209> {51798}- 02-L2 Sent on Port ReplyOut: >>>> MemoryMessage[MissNotify]: Addr:0xp:0003bdc80 Size:0 Serial: 9900 >>>> Core: 0 DStream: true Outstanding Msgs: 1 Requires Ack >>>> 28286<SplitDestinationMapperImpl.cpp:804> {51798}- sys-net-mapper >>>> Dest = 2 (requester):MemoryMessage[MissNotify]: Addr:0xp:0003bdc80 >>>> Size:0 Serial: 9900 Core: 0 DStream: true Outstanding Msgs: 1 Requires >>>> Ack >>>> 28287<SplitDestinationMapperImpl.cpp:495> {51798}- sys-net-mapper >>>> Received Reply from Directory 2 sending to network port 18 - >>>> MemoryMessage[MissNotify]: Addr:0xp:0003bdc80 Size:0 Serial: 9900 >>>> Core: 0 DStream: true Outstanding Msgs: 1 Requires Ack >>>> 28289<CMPCacheImpl.cpp:229> {51798}- 02-L2 Sent on Port SnoopOut: >>>> MemoryMessage[WriteFwd]: Addr:0xp:0003bdc80 Size:0 Serial: 9899 Core: >>>> 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28290<SplitDestinationMapperImpl.cpp:470> {51798}- sys-net-mapper >>>> Received Snoop from Directory 2 sending to network port 19 - >>>> MemoryMessage[WriteFwd]: Addr:0xp:0003bdc80 Size:0 Serial: 9899 Core: >>>> 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28292<MultiNicXImpl.hpp:210> {51799}- 06-nic Packet contains: >>>> MemoryMessage[MissNotify]: Addr:0xp:0003bdc80 Size:0 Serial: 9900 >>>> Core: 0 DStream: true Outstanding Msgs: 1 Requires Ack >>>> 28294<MemoryNetworkImpl.cpp:306> {51799}- Network Received msg From 6 >>>> to 2, on vc 0, serial: 2037 Message = MemoryMessage[MissNotify]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9900 Core: 0 DStream: true >>>> Outstanding Msgs: 1 Requires Ack >>>> 28296<MultiNicXImpl.hpp:210> {51799}- 06-nic Packet contains: >>>> MemoryMessage[WriteFwd]: Addr:0xp:0003bdc80 Size:0 Serial: 9899 Core: >>>> 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28298<MemoryNetworkImpl.cpp:306> {51799}- Network Received msg From 6 >>>> to 0, on vc 0, serial: 2038 Message = MemoryMessage[WriteFwd]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9899 Core: 0 DStream: true >>>> Outstanding Msgs: 0 Requires Ack >>>> 28300<MemoryNetworkImpl.cpp:190> {51803}- Network Delivering msg From >>>> 6 to 2, on vc 6, serial: 2037 Message = MemoryMessage[MissNotify]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9900 Core: 0 DStream: true >>>> Outstanding Msgs: 1 Requires Ack >>>> 28302<MultiNicXImpl.hpp:138> {51803}- 02-nic Packet contains: >>>> MemoryMessage[MissNotify]: Addr:0xp:0003bdc80 Size:0 Serial: 9900 >>>> Core: 0 DStream: true Outstanding Msgs: 1 Requires Ack >>>> 28303<SplitDestinationMapperImpl.cpp:625> {51804}- sys-net-mapper >>>> Received Reply for cache 2 - MemoryMessage[MissNotify]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9900 Core: 0 DStream: true >>>> Outstanding Msgs: 1 Requires Ack >>>> 28304<CacheImpl.cpp:412> {51804}- 02-L1d Received on Port >>>> BackSideIn_Reply: MemoryMessage[MissNotify]: Addr:0xp:0003bdc80 Size:0 >>>> Serial: 9900 Core: 0 DStream: true Outstanding Msgs: 1 Requires Ack >>>> 28305<CacheController.cpp:1053> {51805}- 02-L1d scheduling request >>>> to bank 0: MemoryMessage[MissNotify]: Addr:0xp:0003bdc80 Size:0 >>>> Serial: 9900 Core: 0 DStream: true Outstanding Msgs: 1 Requires Ack >>>> eL1 >>>> 28306<CacheController.cpp:850> {51805}- 02-L1d schedule Back >>>> MemoryMessage[MissNotify]: Addr:0xp:0003bdc80 Size:0 Serial: 9900 >>>> Core: 0 DStream: true Outstanding Msgs: 1 Requires Ack >>>> 28307<CacheController.cpp:1557> {51805}- 02-L1d runBackProcess 4966: >>>> MemoryMessage[MissNotify]: Addr:0xp:0003bdc80 Size:0 Serial: 9900 >>>> Core: 0 DStream: true Outstanding Msgs: 1 Requires Ack >>>> 28308<InclusiveMESI.cpp:635> {51805}- 02-L1d Handle BackProcess: >>>> MemoryMessage[MissNotify]: Addr:0xp:0003bdc80 Size:0 Serial: 9900 >>>> Core: 0 DStream: true Outstanding Msgs: 1 Requires Ack >>>> 28309<StdArray.hpp:584> {51805}- Found block p:0003bdc80 >>>> (p:0003bdc80) in set 114 in state Shared_X >>>> 28311<CacheController.cpp:1681> {51805}- 02-L1d no more work >>>> required for: MemoryMessage[MissNotify]: Addr:0xp:0003bdc80 Size:0 >>>> Serial: 9900 Core: 0 DStream: true Outstanding Msgs: 1 Requires Ack >>>> 28389<MemoryNetworkImpl.cpp:190> {51903}- Network Delivering msg From >>>> 6 to 0, on vc 4, serial: 2038 Message = MemoryMessage[WriteFwd]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9899 Core: 0 DStream: true >>>> Outstanding Msgs: 0 Requires Ack >>>> 28391<MultiNicXImpl.hpp:138> {51903}- 00-nic Packet contains: >>>> MemoryMessage[WriteFwd]: Addr:0xp:0003bdc80 Size:0 Serial: 9899 Core: >>>> 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28392<SplitDestinationMapperImpl.cpp:621> {51904}- sys-net-mapper >>>> Received Snoop for cache 0 - MemoryMessage[WriteFwd]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9899 Core: 0 DStream: true >>>> Outstanding Msgs: 0 Requires Ack >>>> 28393<CacheImpl.cpp:419> {51904}- 00-L1d Received on Port >>>> BackSideIn_Request: MemoryMessage[WriteFwd]: Addr:0xp:0003bdc80 Size:0 >>>> Serial: 9899 Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28394<CacheController.cpp:1053> {51905}- 00-L1d scheduling request >>>> to bank 0: MemoryMessage[WriteFwd]: Addr:0xp:0003bdc80 Size:0 Serial: >>>> 9899 Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack eL1 >>>> 28395<CacheController.cpp:874> {51905}- 00-L1d schedule Back >>>> MemoryMessage[WriteFwd]: Addr:0xp:0003bdc80 Size:0 Serial: 9899 Core: >>>> 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28396<CacheController.cpp:1557> {51905}- 00-L1d runBackProcess 4967: >>>> MemoryMessage[WriteFwd]: Addr:0xp:0003bdc80 Size:0 Serial: 9899 Core: >>>> 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28397<InclusiveMESI.cpp:635> {51905}- 00-L1d Handle BackProcess: >>>> MemoryMessage[WriteFwd]: Addr:0xp:0003bdc80 Size:0 Serial: 9899 Core: >>>> 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28398<StdArray.hpp:584> {51905}- Found block p:0003bdc80 >>>> (p:0003bdc80) in set 114 in state Exclusive >>>> 28399<CacheController.hpp:381> {51905}- Expected to find MAF entry >>>> for p:0003bdc80 but found none. >>>> 28402<CacheController.cpp:1821> {51906}- 00-L1d sendFront (D-1, I-0) >>>> : MemoryMessage[Invalidate]: Addr:0xp:0003bdc80 Size:0 Serial: 9903 >>>> Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28404<CacheImpl.cpp:282> {51906}- 00-L1d Sent on Port FrontSideOut_D >>>> [0]: MemoryMessage[Invalidate]: Addr:0xp:0003bdc80 Size:0 Serial: 9903 >>>> Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28405<ExecuteImpl.cpp:371> {51906}- 00-execute EX received mem >>>> request MemoryMessage[Invalidate]: Addr:0xp:0003bdc80 Size:0 Serial: >>>> 9903 Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28406<ExecuteImpl.cpp:1423> {51907}- 00-execute EX Issuing memory >>>> reply: MemoryMessage[Invalidate Ack]: Addr:0xp:0003bdc80 Size:0 >>>> Serial: 9905 Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28407<CacheImpl.cpp:172> {51907}- 00-L1d Received on Port >>>> FrontSideIn(Snoop) [0]: MemoryMessage[Invalidate Ack]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9905 Core: 0 DStream: true >>>> Outstanding Msgs: 0 Requires Ack >>>> 28412<CacheController.cpp:1053> {51907}- 00-L1d scheduling request >>>> to bank 0: MemoryMessage[Invalidate Ack]: Addr:0xp:0003bdc80 Size:0 >>>> Serial: 9905 Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> eL1 >>>> 28413<CacheController.cpp:964> {51907}- 00-L1d schedule Snoop >>>> MemoryMessage[Invalidate Ack]: Addr:0xp:0003bdc80 Size:0 Serial: 9905 >>>> Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28414<CacheController.cpp:1442> {51907}- 00-L1d runSnoopProcess >>>> 4968: MemoryMessage[Invalidate Ack]: Addr:0xp:0003bdc80 Size:0 Serial: >>>> 9905 Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28415<InclusiveMESI.cpp:1847> {51907}- 00-L1d Snoop message: >>>> MemoryMessage[Invalidate Ack]: Addr:0xp:0003bdc80 Size:0 Serial: 9905 >>>> Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28416<StdArray.hpp:584> {51907}- Found block p:0003bdc80 >>>> (p:0003bdc80) in set 114 in state Exclusive >>>> 28417<InclusiveMESI.cpp:1833> {51907}- 00-L1d Removing Snoop Buffer >>>> entry after receiving final reply: MemoryMessage[FwdReplyWritable]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9899 Core: 0 DStream: true >>>> Outstanding Msgs: 0 Requires Ack >>>> 28421<CacheController.cpp:1864> {51909}- 00-L1d sendBack_Snoop >>>> MemoryMessage[FwdReplyWritable]: Addr:0xp:0003bdc80 Size:0 Serial: >>>> 9899 Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28422<CacheController.cpp:1869> {51909}- 00-L1d Using REPLY channel >>>> sendBack_SnoopMemoryMessage[FwdReplyWritable]: Addr:0xp:0003bdc80 >>>> Size:0 Serial: 9899 Core: 0 DStream: true Outstanding Msgs: 0 Requires >>>> Ack >>>> 28425<CacheImpl.cpp:441> {51909}- 00-L1d Sent on Port >>>> BackSideOut(Reply): MemoryMessage[FwdReplyWritable]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9899 Core: 0 DStream: true >>>> Outstanding Msgs: 0 Requires Ack >>>> 28426<SplitDestinationMapperImpl.cpp:804> {51909}- sys-net-mapper >>>> Dest = 2 (requester):MemoryMessage[FwdReplyWritable]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9899 Core: 0 DStream: true >>>> Outstanding Msgs: 0 Requires Ack >>>> 28427<SplitDestinationMapperImpl.cpp:418> {51909}- sys-net-mapper >>>> Received Reply from cache 0 sending to network port 0 - >>>> MemoryMessage[FwdReplyWritable]: Addr:0xp:0003bdc80 Size:0 Serial: >>>> 9899 Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28441<MultiNicXImpl.hpp:210> {51910}- 00-nic Packet contains: >>>> MemoryMessage[FwdReplyWritable]: Addr:0xp:0003bdc80 Size:0 Serial: >>>> 9899 Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28443<MemoryNetworkImpl.cpp:306> {51910}- Network Received msg From 0 >>>> to 2, on vc 0, serial: 2042 Message = >>>> MemoryMessage[FwdReplyWritable]: Addr:0xp:0003bdc80 Size:0 Serial: >>>> 9899 Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28815<MemoryNetworkImpl.cpp:190> {52033}- Network Delivering msg From >>>> 0 to 2, on vc 6, serial: 2042 Message = >>>> MemoryMessage[FwdReplyWritable]: Addr:0xp:0003bdc80 Size:0 Serial: >>>> 9899 Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28817<MultiNicXImpl.hpp:138> {52033}- 02-nic Packet contains: >>>> MemoryMessage[FwdReplyWritable]: Addr:0xp:0003bdc80 Size:0 Serial: >>>> 9899 Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28818<SplitDestinationMapperImpl.cpp:625> {52034}- sys-net-mapper >>>> Received Reply for cache 2 - MemoryMessage[FwdReplyWritable]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9899 Core: 0 DStream: true >>>> Outstanding Msgs: 0 Requires Ack >>>> 28819<CacheImpl.cpp:412> {52034}- 02-L1d Received on Port >>>> BackSideIn_Reply: MemoryMessage[FwdReplyWritable]: Addr:0xp:0003bdc80 >>>> Size:0 Serial: 9899 Core: 0 DStream: true Outstanding Msgs: 0 Requires >>>> Ack >>>> 28820<CacheController.cpp:1053> {52035}- 02-L1d scheduling request >>>> to bank 0: MemoryMessage[FwdReplyWritable]: Addr:0xp:0003bdc80 Size:0 >>>> Serial: 9899 Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> eL1 >>>> 28821<CacheController.cpp:850> {52035}- 02-L1d schedule Back >>>> MemoryMessage[FwdReplyWritable]: Addr:0xp:0003bdc80 Size:0 Serial: >>>> 9899 Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28822<CacheController.cpp:1557> {52035}- 02-L1d runBackProcess 4988: >>>> MemoryMessage[FwdReplyWritable]: Addr:0xp:0003bdc80 Size:0 Serial: >>>> 9899 Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28823<InclusiveMESI.cpp:635> {52035}- 02-L1d Handle BackProcess: >>>> MemoryMessage[FwdReplyWritable]: Addr:0xp:0003bdc80 Size:0 Serial: >>>> 9899 Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28824<StdArray.hpp:584> {52035}- Found block p:0003bdc80 >>>> (p:0003bdc80) in set 114 in state Shared_X >>>> 28831<CacheController.cpp:1864> {52037}- 02-L1d sendBack_Snoop >>>> MemoryMessage[UpgradeAck]: Addr:0xp:0003bdc80 Size:0 Serial: 9940 >>>> Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28832<CacheController.cpp:1869> {52037}- 02-L1d Using REPLY channel >>>> sendBack_SnoopMemoryMessage[UpgradeAck]: Addr:0xp:0003bdc80 Size:0 >>>> Serial: 9940 Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28839<CacheImpl.cpp:441> {52037}- 02-L1d Sent on Port >>>> BackSideOut(Reply): MemoryMessage[UpgradeAck]: Addr:0xp:0003bdc80 >>>> Size:0 Serial: 9940 Core: 0 DStream: true Outstanding Msgs: 0 Requires >>>> Ack >>>> 28840<SplitDestinationMapperImpl.cpp:813> {52037}- sys-net-mapper >>>> Dest = 6 (dirIndex2NodeIndex(2)):MemoryMessage[UpgradeAck]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9940 Core: 0 DStream: true >>>> Outstanding Msgs: 0 Requires Ack >>>> 28841<SplitDestinationMapperImpl.cpp:418> {52037}- sys-net-mapper >>>> Received Reply from cache 2 sending to network port 6 - >>>> MemoryMessage[UpgradeAck]: Addr:0xp:0003bdc80 Size:0 Serial: 9940 >>>> Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28843<MultiNicXImpl.hpp:210> {52038}- 02-nic Packet contains: >>>> MemoryMessage[UpgradeAck]: Addr:0xp:0003bdc80 Size:0 Serial: 9940 >>>> Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28845<MemoryNetworkImpl.cpp:306> {52038}- Network Received msg From 2 >>>> to 6, on vc 0, serial: 2047 Message = MemoryMessage[UpgradeAck]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9940 Core: 0 DStream: true >>>> Outstanding Msgs: 0 Requires Ack >>>> 28860<MemoryNetworkImpl.cpp:190> {52041}- Network Delivering msg From >>>> 2 to 6, on vc 6, serial: 2047 Message = MemoryMessage[UpgradeAck]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9940 Core: 0 DStream: true >>>> Outstanding Msgs: 0 Requires Ack >>>> 28862<MultiNicXImpl.hpp:138> {52041}- 06-nic Packet contains: >>>> MemoryMessage[UpgradeAck]: Addr:0xp:0003bdc80 Size:0 Serial: 9940 >>>> Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28867<SplitDestinationMapperImpl.cpp:650> {52042}- sys-net-mapper >>>> Received Reply for Directory 2 - MemoryMessage[UpgradeAck]: >>>> Addr:0xp:0003bdc80 Size:0 Serial: 9940 Core: 0 DStream: true >>>> Outstanding Msgs: 0 Requires Ack >>>> 28868<CMPCacheImpl.cpp:183> {52042}- 02-L2 Received on Port Reply_In >>>> : MemoryMessage[UpgradeAck]: Addr:0xp:0003bdc80 Size:0 Serial: 9940 >>>> Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28869<CMPCacheController.hpp:124> {52042}- 02-L2reserveSnoopOut(1): >>>> ProcReply: NoAction, snoop reservations: 0, request reservations: 0, >>>> reply reservations: 0, MemoryMessage[UpgradeAck]: Addr:0xp:0003bdc80 >>>> Size:0 Serial: 9940 Core: 0 DStream: true Outstanding Msgs: 0 Requires >>>> Ack >>>> 28870<CMPCacheController.cpp:297> {52042}- 02-L2 Scheduled Reply: >>>> MemoryMessage[UpgradeAck]: Addr:0xp:0003bdc80 Size:0 Serial: 9940 >>>> Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28871<CMPCacheController.cpp:582> {52042}- 02-L2 runReplyProcess: >>>> MemoryMessage[UpgradeAck]: Addr:0xp:0003bdc80 Size:0 Serial: 9940 >>>> Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> 28872<NonInclusiveMESIPolicy.cpp:1233> {52042}-<undefined> Assertion >>>> failed: ((!(maf->transport()[MemoryMessageTag]->type() == >>>> MemoryMessage::UpgradeReq))) : Matching MAF is not an Upgrade. MAF = >>>> MemoryMessage[Write Request]: Addr:0xp:0003bdc80 Size:0 Serial: 9898 >>>> Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack reply = >>>> MemoryMessage[UpgradeAck]: Addr:0xp:0003bdc80 Size:0 Serial: 9940 >>>> Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>> >>>> >>>> >>>> >>>> >>>> >>>> >>>> >>>> >>>> On Mon, Apr 4, 2011 at 3:36 PM, Jason Zebchuk<[email protected]> >>>> wrote: >>>>> >>>>> Hi Song, >>>>> >>>>> First, one question: are you using different cache block sizes for the >>>>> different levels of cache? At the moment the cache hierarchy does not >>>>> support different cache block sizes at different levels, and I can think >>>>> of >>>>> one way that might produce the error you're seeing. If that's not the >>>>> case, >>>>> keep reading. >>>>> >>>>> The message you're seeing indicates that the shared cache received an >>>>> UpgradeAck for a WriteRequest. The sequence of messages should normally >>>>> be >>>>> one of the following: >>>>> >>>>> Normal Case: >>>>> >>>>> requesting L1 sends Upgrade to L2 >>>>> L2 sends MissNotify to requesting L1 and Invalidates to other L1s >>>>> L1s perform Invalidates and send InvalidateAcks to requesting L1 >>>>> requesting L1 sends UpgradeAck to L2 >>>>> >>>>> Fast Case: >>>>> >>>>> requesting L1 sends Upgrade to L2 >>>>> L2 sends UpgradeReply to L1 >>>>> L1 sends UpgradeAck to L2 >>>>> >>>>> Race Case: >>>>> >>>>> L1-a sends Write to L2 >>>>> L1-b sends Upgrade to L2 >>>>> L2 receives Write from L1-a and sends invalidates to L1-b and any other >>>>> sharers >>>>> L2 receives Upgrade from L1-b, sees that the block has been invalidated, >>>>> and >>>>> silently promotes the request to a Write >>>>> L1-a's Write completes and L1-a sends WriteAck to L2 >>>>> L2 receives WriteAck and processes L1-b's request which is now a Write >>>>> >>>>> >>>>> To see exactly what happened, you should re-run your simulation and turn >>>>> on >>>>> debugging messages part way through. The error occurs at cycle 51001, so >>>>> if >>>>> you run for 50000 cycles then run the command >>>>> >>>>> flexus.debug-set-severity "iface" >>>>> >>>>> then keep running, you should see a dump of all of the debug messages. >>>>> You >>>>> can then extract all the debug statements for the address in question and >>>>> see what exactly might have happened. If you email the list with those >>>>> statements, we should be able to resolve your problem. >>>>> >>>>> >>>>> Jason >>>>> >>>>> >>>>> >>>>> On 04/04/2011 4:12 PM, Song Liu wrote: >>>>>> >>>>>> Another error message comes with same config but different flexpoints. >>>>>> >>>>>> 180<SimicsTracer.hpp:491> {45460}- Interrupt handler instruction >>>>>> ignored. So far 1 instructions have been ignored on cpu2 >>>>>> 181<SimicsTracer.hpp:491> {45460}- Interrupt handler instruction >>>>>> ignored. So far 2 instructions have been ignored on cpu2 >>>>>> 182<SimicsTracer.hpp:491> {45460}- Interrupt handler instruction >>>>>> ignored. So far 3 instructions have been ignored on cpu2 >>>>>> 183<SimicsTracer.hpp:491> {45460}- Interrupt handler instruction >>>>>> ignored. So far 4 instructions have been ignored on cpu2 >>>>>> 184<SimicsTracer.hpp:491> {45460}- Interrupt handler instruction >>>>>> ignored. So far 5 instructions have been ignored on cpu2 >>>>>> 185<SimicsTracer.hpp:491> {45460}- Interrupt handler instruction >>>>>> ignored. So far 6 instructions have been ignored on cpu2 >>>>>> 186<SimicsTracer.hpp:491> {45460}- Interrupt handler instruction >>>>>> ignored. So far 7 instructions have been ignored on cpu2 >>>>>> 187<SimicsTracer.hpp:491> {45460}- Interrupt handler instruction >>>>>> ignored. So far 8 instructions have been ignored on cpu2 >>>>>> 188<NonInclusiveMESIPolicy.cpp:1233> {51001}-<undefined> Assertion >>>>>> failed: ((!(maf->transport()[MemoryMessageTag]->type() == >>>>>> MemoryMessage::UpgradeReq))) : Matching MAF is not an Upgrade. MAF = >>>>>> MemoryMessage[Write Request]: Addr:0xp:0003bdc80 Size:0 Serial: 24140 >>>>>> Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack reply = >>>>>> MemoryMessage[UpgradeAck]: Addr:0xp:0003bdc80 Size:0 Serial: 24221 >>>>>> Core: 0 DStream: true Outstanding Msgs: 0 Requires Ack >>>>>> >>>>>> Song >>>>>> >>>>>> On Thu, Mar 31, 2011 at 11:05 PM, Song Liu<[email protected]> wrote: >>>>>>> >>>>>>> Hi all, >>>>>>> >>>>>>> I am trying to run flexus_test_app with 4 x86 in-order processor cores. >>>>>>> >>>>>>> Besides changing "test_app_threads" and "num_cpus" to 4, I also >>>>>>> changed user-postload.simics: >>>>>>> >>>>>>> -L2:cores = 8, >>>>>>> -net-mapper:Cores = 4, >>>>>>> -net-mapper:Directories = 4, >>>>>>> -network:nodes = 12, >>>>>>> -network:topology-file = 4x3-torus.topology, >>>>>>> >>>>>>> Now I get error >>>>>>> <ExecuteImpl.cpp:666> {4877}- Invalid fill type: eCoherence >>>>>>> >>>>>>> Any suggestion on this error? >>>>>>> >>>>>>> Thanks in advance, >>>>>>> >>>>>>> Song >>>>>>> >>>>> >>>>> >>> >>> >> > <new_assertion.out>
evict_invalidate_race.patch
Description: evict_invalidate_race.patch
