Thank you, Jason.
Finally, concerning L1i caches, I've seen the following configuration
in the default *timing* user-postload.simics file:
### ufetch
# uFetch [timing]
flexus.set "-ufetch:associativity" "2" #
"ICache associativity" (Associativity)
flexus.set "-ufetch:iline" "64" #
"Icache line size in bytes" (ICacheLineSize)
flexus.set "-ufetch:size" "32768" #
"ICache size in bytes" (Size)
Which size does "iline" refer to? To the whole 2-way set, or to the
block specifically?
By reading the description, I understand that the "cache line" refers
to the set as a whole, so each block has a size of 32 bytes, whereas in
all other caches in trace/timing configurations, block size is defined
at 64 bytes.
-George
On Mon, 02 May 2011 11:32:44 -0400, Jason Zebchuk wrote:
Hi George,
You are mostly right.
Eviction (clean) can come from the L1d as well. It implies that the
block was unmodified in the L1d but the L1d did not have write
permissions. This will occur for blocks that are shared between
multiple L1 caches.
Otherwise you are correct.
Jason
