Stavros, Thanks for your replies. // Naderan *Mahmood;
----- Original Message ----- From: Volos Stavros <[email protected]> To: Mahmood Naderan <[email protected]> Cc: simflex <[email protected]> Sent: Wednesday, September 21, 2011 7:47 PM Subject: Re: effect of component delay on IPC Dear Mahmood, As I said in one of my previous emails, reading the code carefully will answer all your questions. The Cache component, used for the L1 cache, has the following parameters (refer to Cache.hpp): PARAMETER( TagLatency, uint32_t, "Total latency of tag pipeline", "tag_lat", 1 ) PARAMETER( TagIssueLatency, uint32_t, "Minimum delay between issues to tag pipeline", "dup_tag_issue_lat", 0 ) PARAMETER( DataLatency, uint32_t, "Total latency of data pipeline", "data_lat", 1 ) PARAMETER( DataIssueLatency, uint32_t, "Minimum delay between issues to data pipeline", "data_issue_lat", 0 ) The CmpCache component, used for a shared L2 cache, has the following parameters (refer to CmpCache.hpp): PARAMETER( DirLatency, int, "Total latency of directory lookup", "dir_lat", 1 ) PARAMETER( DirIssueLatency, int, "Minimum delay between issues to the directory", "dir_issue_lat", 0 ) PARAMETER( TagLatency, int, "Total latency of tag array lookup", "tag_lat", 1 ) PARAMETER( TagIssueLatency, int, "Minimum delay between issues to the tag array", "tag_issue_lat", 0 ) PARAMETER( DataLatency, int, "Total latency of data array lookup", "data_lat", 1 ) PARAMETER( DataIssueLatency, int, "Minimum delay between issues to the data array", "data_issue_lat", 0 ) Regards, -Stavros On Sep 10, 2011, at 3:11 PM, Mahmood Naderan wrote: > Dear Stavros,>Implementation of other timing components may be more complex. > > From what you said and what I found in the code, only main memory delay is > considered in Flexus. No L1 and L2 delay is accounted. Is that right? > > Thanks > // Naderan *Mahmood; > > > ________________________________ > From: Volos Stavros <[email protected]> > To: Mahmood Naderan <[email protected]> > Cc: simflex <[email protected]> > Sent: Friday, August 5, 2011 2:55 AM > Subject: Re: effect of component delay on IPC > > > Dear Mahmood, > > Flexus is a cycle-driven simulator meaning that each component moves forward > upon > receiving a clock tick. This is implemented by the drive function for every > component. This > function is called once per cycle in the timing simulator. Please read the > slides of the following > tutorial beginning from slide 82 for more information. > > http://parsa.epfl.ch/simflex/doc/SimFlex-tutorial-isca2006.pdf > > In few words, the MemoryLoopback component pushes memory requests into the > outQueue > with a delay of the memory latency - 1 cycle (the code explains why > decrementing the latency > by 1 cycle). The enqueue function which is implemented in the file > Common/MessageQueues.hpp > pushes the memory request and the cycle time in which the request will be > ready. The component's > drive function which is called once per cycle checks which messages are ready > (i.e., the cycle time > is smaller or equal than the ready cycle time of the message). In case it's > ready the message is dequeued. > > Implementation of other timing components may be more complex. > > Navigating through the code is the best way to understand how Flexus works. > The debugging mode can > provide more insight in case you cannot follow the code paths. > > Regards, > -Stavros. > > On Jul 30, 2011, at 8:48 AM, Mahmood Naderan wrote: > > Hi >> How does flexus take memory delay into account for IPC calculation? I want >> to set a delay for my component and see the effect on IPC. >> >> For memory, I see the delay is defined as >> PARAMETER( Delay, int, "Access time", "time", 1 ) >> >> The only thing I think is related to that is >> >> outQueue->enqueue(aMessageTransport,cfg.Delay -1); >> >> >> Any more information about that? thanks >> >> // Naderan *Mahmood; >>
