Are TSOB and SSB the same to the items used in paper "Mechanisms for Store-wait–free Multiprocessors" (ISCA-07)? But I think SSB should be different -- Because SSB(scalable store buffer) in the paper uses L1 to store private data, and I do not think the simulator does this.
If we set flexus.set "-uarch:naw_bypass_sb" "false" then theSBNAWCount is always 0? The relations of MemQueue, LSQ, SB and SSB are still not clear to me. Especially, what is SSB, and what is the relation between SB and SSB? I would appreciate it if someone can explain briefly on them. Thanks. 2011/11/6 Jerry <[email protected]> > > Hi, > > I am reading code of uArch component. There are some structure names not > clear to me. Can somebody briefly explain them to me? Thanks. > > SB should be store buffer, SRB should be speculative retirement buffer. > > But what is TSOB and SSB? > In addition, there is memory queue -- theMemQueue. What does it keep? It > seems that it is related to LSQ, SB and SBNAW(store buffer > non-allocating-write??), because there is an assertion > > DBG_Assert( theLSQCount + theSBCount + theSBNAWCount == > static_cast<long>(theMemQueue.size()) ); > > What are their relations? > > Thanks. > >
