Greetings.
I have been trying to become familar with Simflex, aiming to run some
simulations on different NUCA configurations. While I have found the
sequence of actions when a hit on an L1 occurs, I am having some trouble
finding out how exactly a miss is implemented.
To become more specific:
let's assume we are using the CMP.L2SharedNUCA.Inorder simulator, with
4 tiles. I have noticed, for instance, that once a request on tile's 0
L1 misses, a new MemoryTransport is created and forwarded through the
NIC to the appropriate L2 node (not tile 0's L2 neccessarilly). This is
the point where I cannot figure out what is happening, how/where the
L2-destination is decided. I can track the process until we find out
that the request on the L1 misses and I can see the new MemoryTransport
that travels from the L1 to the appropriate L2 tile through the nic, but
I am not able to find what happens in between, how and where this
transport is created.
The request's path, as I have seen:
- CacheController's "handleRequestTransport" calls
BaseCacheController's "handleRequestTransport"
- This calls BaseCacheController's "examineRequest"
- This calls MESI's "doRequest", which does a lookup in the array and
determines whether it is a hit or miss
All these functions are passing a MemoryTransport as a parameter to
each other. I suppose that, when a miss is identified, a new
MemoryTransport is created somewhere and by someone, its destination is
determined and then it is released on the nic to get to its (L2)
destination. Have I overlooked something? Could anyone please direct me
where to find this? I would be really grateful, since I am stuck at this
point for quite some time. I want to experiment on changing the mapping
on the L2, so this point is of crucial importance.
Thank you in advance
Alexandros Daglis
