Hi Shan, The Snoop buffer is related to coherence, as you inferred. Because we have a mutli-level cache hierarchy and queues between each cache level, our caches need to deal with the fact that Invalidation and Downgrade messages take time to propagate up and down the heirarchy. Futhermore, there can be races between request messages on the way down the hierarchy at the same time invalidations or downgrades on the way up.
The snoop buffer keeps track of Invalidation and Downgrade messages that have propagated up (towards the CPU) past a particular cache level, for which acknowledgements (InvAck, InvUpdateAck, ...) have not yet propageted down the hierarchy (towards memory). Special actions have to be taken if requests and snoops for the same address are simultaneously outstanding, in order to preserve coherence and legal memory order. For the same reasons, we also have two virtual channels (Request and Snoop) for messages which flow from the CPU through the cache hierarchy towards memory. Messages travelling in the Snoop channel may overtake messages travelling in the Request channel, but not vice-versa. Regards, -Tom Wenisch On Sun, 23 Oct 2005, shan wrote: > Hi, > I am reading the cache related code. I am not sure what the 'snoopBuffer' > is. At first I thought this is something related to snooping cache coherence > protocol, but it seems not. ... what is this? > Thanks > Shan > > From penglu01 at hotmail.com Mon Oct 24 23:57:44 2005 From: penglu01 at hotmail.com (lu peng) List-Post: [email protected] Date: Mon Oct 24 23:57:45 2005 Subject: [Simflex] Installation setting problem In-Reply-To: <pine.lnx.4.53l-ece.cmu.edu.0510211656330.15...@dalmore.ece.cmu.edu> Message-ID: <[email protected]> An HTML attachment was scrubbed... URL: http://sos.ece.cmu.edu/pipermail/simflex/attachments/20051025/f64ac2a3/attachment.html From shanlu at cs.uiuc.edu Tue Oct 25 13:14:52 2005 From: shanlu at cs.uiuc.edu (shan) List-Post: [email protected] Date: Tue Oct 25 13:26:59 2005 Subject: [Simflex] CMP cache coherence protocol question In-Reply-To: <pine.lnx.4.53l-ece.cmu.edu.0510232331130.30...@dalmore.ece.cmu.edu> Message-ID: <[email protected]> Hi Tom, Is there some document or something explaining the cache coherence for CMP in the SimFlex? I know the general MOSI protocol and I read the PiranhaCache-Controller files, but maybe because I am not very familiar with the CMP and cache coherence, I still do not understand this module very well. The document said the SimFlex CMP has private L1 and shared L2. Does that mean there are only one L2 and only one directory shared by all cores? Is the M-E-S-I states shared by all cores? Does the L1 cache in CMP need to be configured somehow different from that in the Uni-processor scenario? I didn't find the difference in the wiring.cpp. However, shouldn't the L1 cache at least be write-through instead of write-back? Sorry to take your time with so many questions. Thanks Shan
