Hi,
I am trying to run the x86 CMP module. I am not sure if what I did is
correct.
I used the simics enterprise-4p.simics macro and didn't change any
configuration on the flexus side (should I change any configuration at the
flexus side?)
When I load the module, it shows:
1 <startup.cpp:107> {0}- Initializing Flexus.
..
2 <ComponentManager.cpp:80> {0}- Instantiating system with a width factor
of: 4
3 <InorderSimicsFeederImpl.cpp:290> (feeder[0]) {0}- Initializing
InorderSimicsFeeder.
3 <InorderSimicsFeederImpl.cpp:290> (feeder[0]) {0}- Initializing
InorderSimicsFeeder.
4 <InorderSimicsFeederImpl.cpp:338> (feeder[<undefined>]) {0}- Connecting:
cpu0
5 <InorderSimicsFeederImpl.cpp:338> (feeder[<undefined>]) {0}- Connecting:
cpu1
6 <InorderSimicsFeederImpl.cpp:338> (feeder[<undefined>]) {0}- Connecting:
cpu2
7 <InorderSimicsFeederImpl.cpp:338> (feeder[<undefined>]) {0}- Connecting:
cpu3
...
Why above feeder index is 'undefined', does it imply I made some mistake in
configuration?
Then I type 'continue'. After a while, the screen shows:
25 <MemoryMapImpl.cpp:319> {0}- Assigned 0 pages.
26 <flexus.cpp:240> {0}- Timestamp: 2005-Oct-25 19:49:10
27 <flexus.cpp:326> {108288}- Watchdog timer expired. No progress by CPU 0
for 100215cycles
28 <flexus.cpp:330> (<undefined>[<undefined>]) {108288}- Assertion failed:
((!(theWatchdogCounts[i] < theWatchdogTimeout + 10))) : Watchdog timer
expired. No progress by CPU 0 for 100215cycles
*** Simics getting shaky, switching to 'safe' mode.
*** Simics (main thread) received an abort signal, probably an assertion.
<Simics is running in 'safe' mode>
I checked the assertion at flexus.cpp line 330. It seems that if the cpu
idles for some time, the assertion would fail. Yes? I temporarily removed
the assertion and continues. And get following debug output:
52 <ExecuteImpl.cpp:341> (execute[2]) {250546}- EX received Reply
MemoryMessage[Store Reply]: Addr:0xp:00ff3ffac Size:8 Core: 0
53 <ExecuteImpl.cpp:1287> (execute[2]) {250548}- EX Issuing memory request:
MemoryMessage[Store Request]: Addr:0xp:00ff3ffa8 Size:8 Core: 0
Again, I fear there is something wrong. The reason is, based on the debug
output only execute[2] is doing work, however, all MemoroyMessage shows
'core 0'. Is this something abnormal?
:-) sorry for the whole bunch of questions :-).
Thanks very much
Shan
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From jsmolens+ at ece.cmu.edu Wed Oct 26 01:21:38 2005
From: jsmolens+ at ece.cmu.edu (Jared C. Smolens)
List-Post: [email protected]
Date: Wed Oct 26 13:14:37 2005
Subject: [Simflex] CMP cache coherence protocol question (fwd)
Message-ID: <[email protected]>
Hi Shan,
The idea behind "owner" is to track which cache is responsible for the
last copy of the block in the CMP. This is independent of whether the
line is modifiable or not.
The meaning in the M state is clear, since there should only be one cache
with permission to modify the block.
In the S state, the owner isn't important, since all caches are equal.
However, if the line only exists in an L1 (and not the shared L2), the
owner field reflects that. When the line is eventually replaced by the
owner's L1, instead of silently dropping the block, it is then placed in
the L2 as a victim (this becomes the case you described below). As you
correctly said, no caches in the CMP have permission to write to the line
when the directory is in S state. To write, permission must first be
requested from memory.
There is no function named "SendRequest" in the Piranha* code, but you
probably really meant "sendMessage". In all cases, messages in Piranha*
are sent from the perspective of the shared L2 cache (so sending a
message TO the L2 is nonsensical) and there is a well-defined
destination. Here's a quick rundown of the methods that are used to send
messages and what they do:
1) sendBroadcast() - send a message to all L1 sharers within the CMP,
typically used for invalidations. The coreIdx is always set within
sendBroadcast().
2) sendOwnerRequest() - send a message to the L1 owner of the block.
This is only happens when an L1 is the owner and coreIdx is set to the
owner.
3) setupExternalRequest() - send a message to external memory. Here, the
L2 makes an off-chip request. There is no notion of an off-chip core in
this system, therefore none is set.
Cheers,
Jared
Excerpts From "shan" <[email protected]>:
RE: [Simflex] CMP cache coherence p: "shan" <[email protected]>
> I see.
> Emm, I am not sure if I catch the idea.
> My current understanding is, for example, the 'owner' means which L1
or L2
>caches own the writable version of the block. If the current MESI state
is
>'S', then the owner is the L2 cache and the copies of this cache line in
all
>sharer do not have 'modifiable' privilege. Is my understanding correct?
> B.T.W., usually how can I tell what's the receiver of a message from
the
>code? In the cache PiranhaCacheXXX files, there are a lot of
SendRequest,
>are those messages send to L2 cache itself, if the request's coreIndx is
not
>specially set?
>
>Thanks very much
>shan
>
>
>-----Original Message-----
>From: [email protected] [mailto:[email protected]]
On
>Behalf Of Thomas Wenisch
>Sent: Tuesday, October 25, 2005 1:50 PM
>To: [email protected]
>Subject: Re: [Simflex] CMP cache coherence protocol question (fwd)
>
>Hi Shan,
>
>See below. We will try to get the state diagram out soon.
>
>Regards,
>-Tom Wenisch
>
>---------- Forwarded message ----------
>Date: Tue, 25 Oct 2005 13:53:49 -0400 (EDT)
>From: Jared C. Smolens
>To: [email protected]
>Subject: Re: [Simflex] CMP cache coherence protocol question
>
>
>Excerpts From "shan" <[email protected]>:
> [Simflex] CMP cache coherence proto: "shan" <[email protected]>
>>Hi Tom,
>> Is there some document or something explaining the cache coherence
for
>> CMP in the SimFlex? I know the general MOSI protocol and I read the
>>PiranhaCache-Controller files, but maybe because I am not very familiar
>>with the CMP and cache coherence, I still do not understand this module
>>very well.
>
>I am preparing the state diagram for distribution. Stay tuned.
>
>> The document said the SimFlex CMP has private L1 and shared L2. Does
>>that mean there are only one L2 and only one directory shared by all
>>cores?
>
>Yes. We maintain a logical directory at a single, shared L2 in CMPFlex.
>The directory covers all lines in the CMP core.
>
>>Is the M-E-S-I states shared by all cores?
>
>The coherence states (including transient states) are maintained in a
>directory structure at the shared L2. The L1 caches have the same
states
>as in DSMFlex (permutations of Valid, Modifiable, and Dirty bits).
>
>> Does the L1 cache in CMP need to be configured somehow different from
>> that in the Uni-processor scenario?
>
>Yes, there is one difference from the Uhiprocessor/DSMFlex
>configurations: the EvictClean option is set to true in CMPFlex. This
>option causes clean lines to be sent to the L2, instead of being
silently
>dropped on replacement. This models Piranha's use of the shared cache
as
>a large "victim cache" for L1 replacements.
>
>>I didn't find the difference in the
>>wiring.cpp. However, shouldn't the L1 cache at least be write-through
>>instead of write-back?
>
>The private caches are still write-back, but both clean and dirty lines
>are written back to the shared cache on replacement.
>
>> Sorry to take your time with so many questions.
>>
>>Thanks
>>Shan
>
Jared Smolens ----------- Electrical and Computer Engineering
www.rabidpenguin.org ------------- Carnegie Mellon University
jsmolens AT ece.cmu.edu ------ HH A-313 ------ Pittsburgh, PA
