Hi Joe, On Tue, 27 Sep 2005, Babak Falsafi wrote:
> On Sep 27, 2005, at 7:37 PM, Joseph A Tucek wrote: > > > Hello, > > > > My name is Joe Tucek, and I am a student of YY Zhou's at UIUC. We > > were wanting to use your SimFlex tool to do some timing > > simulations, and I had a few questions. > > > > Primarily, there is conflicting information about x86 support, and > > I was wondering what the actual status is. Some places on the > > project site say that x86 is supported, and other places only > > mention SPARC--how well is x86 currently supported for SMP/CMP > > simulation? How accurate is the associated timing model? Also, > > what level of support is there (again, for x86) for different > > coherence methods (ie. snooping/directory based, MSI, MOSI, etc)? We support x86 for in-order simulation. You can use all of our memory system components (uniprocessor, CMP, etc). with both x86 and SPARC. Thus, you can do in-order timing simulation with x86. All of the memory system components implement detailed timing (configurable latencies, queueing delays, etc). Alternatively, if you want to do functional/trace-like simulation, you can enable "fast-mode" in Flexus, which sets all latencies to their minimum values. Our out-of-order execution components only support SPARC. We implement the complete SPARC v9 ISA in our out-of-order core. It would require quite significant effort to support x86 in out-of-order simulation, and that support is not planned right now. The current Flexus release contains memory system components for a uniprocessor and for a CMP. The CMP implements a Piranha-like coherence mechanism to maintain coherence among the private L1 caches. With some fairly simple additions, it is also possible to construct a snooping bus-based multiprocessor with the current release (i.e. an SMP or SMP of CMPs). We also have DSM memory components that implement directory-based coherence using micro-coded coherence protocol engines. We have implemented an aggressive 3-hop MSI-like protocol, again based on Piranha. We can model an arbitrary interconnection network between compute nodes. The DSM components have not been publicly released yet, but will be made available before MICRO (i.e., within the next month or so). All of these components work with both x86 and SPARC (or, in principle, any other ISA that Simics supports). > > > > Finally, is there a student or other place where I could send some > > additional questions in the future as issues come up? Send your questions to [email protected]. We do our best to get back to you within 24 hours. Best Regards, -Tom Wenisch Computer Architecture Lab Carnegie Mellon University From twenisch at ece.cmu.edu Thu Sep 29 11:58:50 2005 From: twenisch at ece.cmu.edu (Thomas Wenisch) List-Post: [email protected] Date: Thu Sep 29 11:58:37 2005 Subject: [Simflex] Re: Disk Images, In-Reply-To: <[email protected]> References: <[email protected]> Message-ID: <pine.lnx.4.53l-ece.cmu.edu.0509291157480.14...@dalmore.ece.cmu.edu> Hi Arrvindh, I believe you will need to use either ext3fs or reiserfs to exceed 2GB. We use reiserfs on all our machines. Regards, -Tom Wenisch On Thu, 29 Sep 2005, Arrvindh Shriraman wrote: > Hi Tom, > > How do you get simics to use disk images > 10G (I presume that you are > doing that with your Database benchmarks) since linux ext2fs doesn't > recognize file sizes greater than 2G. > > With Regards, > > -- > Arrvindh Shriraman > Computer Science Dept > University of Rochester > www.cs.rochester.edu/u/ashriram > From twenisch at ece.cmu.edu Thu Sep 29 12:18:54 2005 From: twenisch at ece.cmu.edu (Thomas Wenisch) List-Post: [email protected] Date: Thu Sep 29 12:18:40 2005 Subject: [Simflex] Re: Simics script In-Reply-To: <[email protected]> References: <[email protected]> Message-ID: <pine.lnx.4.53l-ece.cmu.edu.0509291205070.22...@dalmore.ece.cmu.edu> Hi Arrvindh, The distribution of SimFlex that we made public does not contain all of the DSM components (protocol controller, directory, interconnect model, etc). We will make this public fairly soon (~ one month). In the meantime, with a small amount of coding, you can get a snoopy-coherence MP system up and running. The changes are not in .simics scripts, you need to modify the Flexus wiring file to do this. Start by taking a look at simulators/UniFlex/wiring.cpp and simulators/CMPFlex/wiring.cpp. You will want to create a new simulators/SMPFlex directory, using UniFlex and/or CMPFlex as a starting point. First, try to modify the wiring so that each CPU has its own L2, and its own "MemoryLoopback". This can be accomplished just by modifying wiring.cpp. It will look very similar to the UniFlex wiring. If you hook things up this way, you will have private L2's, but they will not maintain coherence. Try to get this working first. The next step is to create a new component (e.g., SMPBus) that sends snoop messages to all of the L2 caches. You can start by copying the code from the CMPCache component to see how to connect to an array of L2's. Whenever this component gets a read request for any address, it needs to send a Downgrade message to all other L2's, and whenever it gets a write, it needs to send an Invalidate message to everyone else. This will maintain coherence across the cache heirarchies. I suggest you spend some time digging through the code I mention above to see if you can understand what I am talking about. Then, you can email the SimFlex list with questions. Regards, -Tom Wenisch Computer Architecture Lab Carnegie Mellon University On Wed, 28 Sep 2005, Arrvindh Shriraman wrote: > Hi Tom, > > Would it be possible for you to send me a sample ".simics" script on how > you set up the DSM configurations.(I am specifically having problems on > how to specify private L2 caches and shared memory). > > Thanks > -- > Arrvindh Shriraman > Computer Science Dept > University of Rochester > www.cs.rochester.edu/u/ashriram > From liutao at ict.ac.cn Fri Sep 30 05:27:41 2005 From: liutao at ict.ac.cn (Liu,Tao) List-Post: [email protected] Date: Fri Sep 30 09:28:34 2005 Subject: [Simflex] Run Benchmarks Message-ID: <[email protected]> Hi, Tom, Could you tell me do you (or your team) have ever run any benchmarks (e.g. SPLASH2, etc.) on the flexus? And is the flexus stable enough for these benchmarks? Another question is: if I want to simulate the benchmarks and self-developed applications on flexus, do I must insert these flexus magic breakpoints (e.g. flexBkp_StartWarmup, flexBkp_StartParallel, etc.) into source code? Thanks! Best Regards, Tao Liu -------------- next part -------------- An HTML attachment was scrubbed... URL: http://sos.ece.cmu.edu/pipermail/simflex/attachments/20050930/9ac51266/attachment.html
