Excerpts From "Abu Saad Papa" <[email protected]>:
Re: [Simflex] Network Topologies in: "Abu Saad Papa" <abu_s...@research.
> I have a few more queries. In the results I am getting a section of
>Nodes-HE-xxxxx and Nodes-RE-xxxxx. I would like to know what this HE and
>RE means as I can see two files in the DSMFlex.OoO namely he.rom and
>re.rom after running make DSMFlex.OoO.
HE stands for "home engine" and RE stands for "remote engine". These are
modeled after components with the same name in the Piranha paper by Barroso
et al, ISCA'00. This paper is a very good reference.
<snip>
> Similarly I am getting some data for sys-network-NetworkLatency VC[1] and
> sys-network-NetworkLatency VC[2]. The total count of VC[0] , VC[1] and
>VC{2] equals to the number of messages received. From this data how will
>I know the total network latency. Also is this network latecny inculsive
>of the sys-cycles. I mean for sys-cycles = 250000 and say 'X' cycles of
>network latency (I don't know how to arrive at 'X' from the obtained
>data) computational latency is 250000 and network latency is 'X' or
>computational latency is 250000-X.
You should use the time breakdown statistics (look for remote memory
latencies) to get the measures you are looking for. The sum of all
breakdown measures should equal sys-cycles (or sys-cycles *
number_of_processors, I can't remember which, but it should be clear from
looking at the data).
As an aside, the VCs are used for different types of messages (in
decreasing order of priority: 2 = acknowlegements, 1 = forwards, 0 =
requests). Using the network latency statistics directly is almost
definitely not what you are loooking for.
- Jared
>
>Abu Saad
>
>>
>> Hi,
>>
>> See responses inline...
>>
>> Excerpts From "Abu Saad Papa" <[email protected]>:
>> [Simflex] Network Topologies in DSM: "Abu Saad Papa"
<abu_s...@research.
>>>Hi,
>>> As part of my research work, I would like to compare the latency of the
>>>interconnection network (connecting the various on-chip cores) and
>>>computational latency of each core. I am assuming a CMP with on-chip
>>>interconnection network. The number of cores on the chip is varying from
>>>2 to the max allowed in Flexus. I have a few clarifications to make
>>>
>>>1) Can I use DSMFlex.OoO for the above work i.e a CMP with on-chip
>>>interconnection network?
>>
>> Yes, this is possible if you scale the on-chip and off-chip memory
>> latencies appropriately. It's also relatively easy to integrate the
>> network simulator into the CMP model (this is preferable).
>> CacheController::doNewRequests() is probably the best place to add it
>> there.
>>
>>>2) I tried DSMFlex.OoO with test application given in the starting guide
>>>with 8-cores and obtained some statistics. I would like to know how to
>>>calculate the network latency from the obtained results? ( are the
>>>latencies given in number of cycles). Anyway I have attached the results
>>> I
>>>obtained at the end of this mail for clarity.
>>
>> The latencies are in processor core cycles. You can change the network
>> latencies in the topology file.
>>
>>>3) What other topologies I can use other than torus (the file I see in
>>>DSMFlex.OoO folder)? What is the procedure to use a topology say a mesh
>>> or
>>>any other topology other than torus?
>>
>> There is a utility for generating these topology files in
>> components/NetShim/testing/
>>
>> Run 'make' from within that directory. The historically-named 'torus'
>> program generates topology files, both mesh and torus varieties.
>> Something
>> along the lines of this should generate a 4x4 mesh:
>>
>> ./torus 16 -m -d mesh16.txt
>>
>> Using -t instead of -m will generate the familiar 2D torus.
>>
>>>4) What is the max no of cores I can use in DSMFlex.OoO?
>>
>> 16 cores has been verified for both the DSM and CMP simulators. Up to
32
>> cores should also work in the CMP, but (to the best of my knowledge)
this
>> has not been tested.
>>
>> - Jared
>>
>>> Thanks in Advance.
>>>
>
>
>
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