Dear Peter, I believe TurboSMARTSim supports only the alpha target. Do you get similar errors when trying to compile for Alpha?
Best Regards, -Thomas Wenisch On Wed, 17 Oct 2007, Û³À´Çí wrote: > Dear all, > > I want to use TurboSMARTSim as my simulator, then use it to get the > simulated time of a program. but when i run 'make config-pisa', 'make', the > command line tells me 'CLK_TCK' could not be declared. my GCC's version is > 4.1.2, my OS is Fedora 6, would you like to help me? > BTW, I want to get the accurate runtime of a program run on a single thread > platform. Would you like to recommend me some available simulators to me? > Any suggestions from you are appreciated. Thanks. > > Best wishes, > > Peter > -------------- next part -------------- _______________________________________________ SimFlex mailing list [email protected] https://sos.ece.cmu.edu/mailman/listinfo/simflex SimFlex web page: http://www.ece.cmu.edu/~simflex From laiqiong.yan at gmail.com Mon Oct 22 11:50:26 2007 From: laiqiong.yan at gmail.com (=?GB2312?B?27PAtMft?=) List-Post: [email protected] Date: Mon Oct 22 13:41:02 2007 Subject: [Simflex] 'CLK_TCK ' do not declare???? In-Reply-To: <[email protected]> References: <[email protected]> <[email protected]> Message-ID: <[email protected]> Dear Thomas, Thanks for your suggestion. But when I recompile it using "make config-alpha, make", the error is as following, /***************************************error**************************************/ gcc -O3 -Wall -c exolex.c exolex.l: ??? 'yylex' ?? exolex.l:132: ??????? 2(?? '_fatal')???????????? exolex.l: ??? 'yy_setstream' ?? exolex.l:204: warning????? 2(?? '_fatal')???????????? rm -f libexo.a ar qcv libexo.a libexo.o exolex.o a - libexo.o a - exolex.o ranlib libexo.a make[1]: Leaving directory `/home/user/ss3/libexo' gcc -o sim-fast `./sysprobe -flags` -O3 -Wall sim-fast.o main.o syscall.o memory.o regs.o loader.o endian.o dlite.o symbol.o eval.o options.o stats.o range.o misc.o storebuf.o machine.o libexo/libexo.a `./sysprobe -libs` -lm -lz /usr/bin/ld: errno: TLS definition in /lib/libc.so.6 section .tbss mismatches non-TLS reference in eval.o /lib/libc.so.6: could not read symbols: Bad value collect2: ld return 1 make: *** [sim-fast] error 1 /**********************************************error******************************************************************/ Would you like to help me ? Thanks you very much. Best wishes, Peter 2007/10/20, Thomas Wenisch <[email protected]>: > > Dear Peter, > > I believe TurboSMARTSim supports only the alpha target. Do you get > similar errors when trying to compile for Alpha? > > Best Regards, > -Thomas Wenisch > > On Wed, 17 Oct 2007, ?????? wrote: > > > Dear all, > > > > I want to use TurboSMARTSim as my simulator, then use it to get the > > simulated time of a program. but when i run 'make config-pisa', 'make', > the > > command line tells me 'CLK_TCK' could not be declared. my GCC's version > is > > 4.1.2, my OS is Fedora 6, would you like to help me? > > BTW, I want to get the accurate runtime of a program run on a single > thread > > platform. Would you like to recommend me some available simulators to > me? > > Any suggestions from you are appreciated. Thanks. > > > > Best wishes, > > > > Peter > > > _______________________________________________ > SimFlex mailing list > [email protected] > https://sos.ece.cmu.edu/mailman/listinfo/simflex > SimFlex web page: http://www.ece.cmu.edu/~simflex > > _______________________________________________ > SimFlex mailing list > [email protected] > https://sos.ece.cmu.edu/mailman/listinfo/simflex > SimFlex web page: http://www.ece.cmu.edu/~simflex > > -- Best wishes, Yours sincerely YAN, Laiqiong -------------- next part -------------- An HTML attachment was scrubbed... URL: http://sos.ece.cmu.edu/pipermail/simflex/attachments/20071022/d4d417bd/attachment.html From twenisch at eecs.umich.edu Fri Oct 26 12:40:18 2007 From: twenisch at eecs.umich.edu (Thomas Wenisch) List-Post: [email protected] Date: Fri Oct 26 12:54:18 2007 Subject: [Simflex] Possible AMD platform problem with test application in the Flexus-Getting-Started-2.1.1 guide In-Reply-To: <[email protected]> References: <[email protected]> Message-ID: <[email protected]> Hi all, FYI I have determined the source of this problem - Flexus's built in profiling support (for profiling the speed of the simulator) uses the rdtsc instruction, which appears to cause a crash on AMD machines. The crash below happens during the profile processing (as indicated by debug output line 42). One quick fix is to comment out the calls to "writeProfile" and "resetProfile" in core/flexus.cpp within the function "advanceCycles". There may be better fixes, but this should get you past the crash. Best Regards, -Thomas Wenisch On Thu, 18 Oct 2007, XXXXXXXXX XXXXXXXX (Kavvadias Stamatis) wrote: > Hi, > > I have a problem running the test application (in flexus-test-app directory > of the distribution). When running ./create-initial-flexpoint TraceFlex, I > get: > > --------------------------------------------------------------- > {0} godzilla5.ics.forth.gr | STEVEN # ./create-initial-flexpoint TraceFlex > Starting initial flexpoint creation of flexus_test with TraceFlex in > /scratch/kavadias/SimFLEX/flexus-2.1.1/flexus-test-app/runs/kavadias-TraceFlex-18Oct07-152725 > Launching job > Opening debug output file: debug.out > Opening debug output file: stats.out > Successfully parsed debug configurations from debug.cfg > Initializing Flexus::ConfigurationManager...done > Initializing Flexus::ComponentManager...done > Entered init_local > 1 <startup.cpp:109> {0}- Initializing Flexus. > > Flexus (C) 2006 The SimFlex Project > Eric Chung, Brian Gold, Nikos Hardavellas, Jangwook Kim, Ippokratis Pandis, > Minglong Shao, Jared Smolens, Stephen Somogyi, Thomas Wenisch, Roland > Wunderlich > Anastassia Ailamaki, Babak Falsafi and James C. Hoe. > > Flexus Simics simulator - Built as TraceFlex 2.1 > > 2 <ComponentManager.cpp:81> {0}- Instantiating system with a width factor of: > 1 > 3 <SimicsTracer.cpp:555> {0}- Initializing SimicsTracerManager. > 4 <SimicsTracer.cpp:662> {0}- Connecting: cpu0 > 5 <SimicsTracer.cpp:665> {0}- DecoupledFeeder connects Flexus cpu0 to Simics > object cpu0 > warning: converting string->object: cpu0 > 6 <SimicsTracer.cpp:684> {0}- Creating DMA map object > 7 <SimicsTracer.cpp:726> {0}- Connecting to DMA memory map > 8 <SimicsTracer.cpp:567> {0}- Done initializing SimicsTracerManager. > 9 <BPWarm.hpp:55> {0}- bpwarm port InsnOut is not wired > 10 <FastCache.hpp:69> {0}- L1d port SnoopOut is not wired > 11 <FastCache.hpp:69> {0}- L1d port Reads is not wired > 12 <FastCache.hpp:69> {0}- L1d port Writes is not wired > 13 <FastCache.hpp:69> {0}- L1i port SnoopOut is not wired > 14 <FastCache.hpp:69> {0}- L1i port Reads is not wired > 15 <FastCache.hpp:69> {0}- L1i port Writes is not wired > 16 <FastCache.hpp:69> {0}- L2 port Reads is not wired > 17 <FastCache.hpp:69> {0}- L2 port Writes is not wired > 18 <FastBus.hpp:73> {0}- bus port Writes is not wired > 19 <FastBus.hpp:73> {0}- bus port Reads is not wired > 20 <FastBus.hpp:73> {0}- bus port Evictions is not wired > 21 <FastBus.hpp:73> {0}- bus port Flushes is not wired > 22 <FastBus.hpp:73> {0}- bus port Invalidations is not wired > 23 <wiring.cpp:79> {0}- initializing Parameters... > 24 <flexus.cpp:369> {0}- Set stat interval to : 10000000 > 25 <flexus.cpp:389> {0}- Set profile interval to : 10000000 > 26 <flexus.cpp:394> {0}- Set timestamp interval to : 1000000 > Warning: The 'flexus-TraceFlex-v9-iface-gcc' module unexpectedly defined the > 'DMATracer' class > Opening debug output file: termination.out > Successfully parsed debug configurations from termination.dbg.cfg > 27 <ComponentManager.cpp:96> {0}- Initalizing components... > 28 <SimicsTracer.cpp:602> {0}- >>>>> OK > 29 <flexus.cpp:262> {0}- Timestamp: 2007-Oct-18 15:27:26 > 30 <FastCacheImpl.cpp:123> {0}- Running with MT width 1 > 31 <flexus.cpp:262> {1000000}- Timestamp: 2007-Oct-18 15:27:28 > 32 <flexus.cpp:262> {2000000}- Timestamp: 2007-Oct-18 15:27:29 > 33 <flexus.cpp:262> {3000000}- Timestamp: 2007-Oct-18 15:27:31 > 34 <flexus.cpp:262> {4000000}- Timestamp: 2007-Oct-18 15:27:33 > 35 <flexus.cpp:262> {5000000}- Timestamp: 2007-Oct-18 15:27:35 > 36 <flexus.cpp:262> {6000000}- Timestamp: 2007-Oct-18 15:27:36 > 37 <flexus.cpp:262> {7000000}- Timestamp: 2007-Oct-18 15:27:38 > 38 <flexus.cpp:262> {8000000}- Timestamp: 2007-Oct-18 15:27:40 > 39 <flexus.cpp:262> {9000000}- Timestamp: 2007-Oct-18 15:27:42 > 40 <flexus.cpp:262> {10000000}- Timestamp: 2007-Oct-18 15:27:43 > 41 <flexus.cpp:273> {10000000}- Saving stats at: 10000000 > 42 <flexus.cpp:292> {10000000}- Writing profile at: 10000000 > (*** Simics ***) Simics getting shaky, switching to 'safe' mode. > Simics (main thread) received a segmentation fault. Will try to recuperate. > simics> > > [After pressing Ctrl-D] > > ./run-job: line 259: cd: flex_state_out: No such file or directory > all.measurement.out > configuration.out > configuration.simics > console.out > debug.cfg > debug.out > go.sh > go.tmp > iteration.trace.cfg > load-flexpoint.simics > load.simics > postload.simics > preload.simics > profile.out > save.simics > start.noflexus.simics > start.simics > stats_db.out.gz > stats.out > termination.dbg.cfg > termination.out > trace-debug.cfg > > --------------------------------------------------------------- > > > I am running flexus on a dual AMD Opteron machine. > > The OS is: Red Hat Enterprise Linux Server release 5 (Tikanga) > (Red Hat 4.1.1-52) > > I installed gcc-4.1.0 (just in case) and build flexus with that: > > --------------------------------------------------------------- > {0} godzilla5.ics.forth.gr | STEVEN # > /scratch/kavadias/gcc-4.1.0/bin/g++-4.1.0 -v > Using built-in specs. > Target: x86_64-unknown-linux-gnu > Configured with: ../gcc-4.1.0/configure --program-suffix=-4.1.0 > --with-prefix=/home/gcc-4.1.0 --with-suffix=-4.1.0 --disable-threads > --enable-languages=c,c++ > Thread model: single > gcc version 4.1.0 > --------------------------------------------------------------- > > My simics version is (the oldest I could download): > > --------------------------------------------------------------- > {0} godzilla5.ics.forth.gr | STEVEN # ./simics --version > Simics simics-2.2.19 (Tue Aug 16 20:23:17 CEST 2005) > C-compiler: gcc gcc (GCC) 3.4.1 > C++-compiler: g++ g++ (GCC) 3.4.1 > (HOST_64_BIT) > > --------------------------------------------------------------- > > I had to change in makefile.defs: > GCC_LIB_PATH=$(GCC_PATH)/lib > with > GCC_LIB_PATH=$(GCC_PATH)/lib64 > and add -fPIC to compilation flags in order to make TraceFlex, UniFlex.OoO > and stat-manager > > > Because of a known problem with make 3.81 > (https://sos.ece.cmu.edu/pipermail/simflex/2006-July/000236.html) > I had to make core and core-simics manually: > (make core SELECTED_CC=gcc TARGET_PLATFORM=v9 SELECTED_DEBUG=iface > FLEXUS_ROOT=/scratch/kavadias/SimFLEX/flexus-2.1.1 > and > make simics SELECTED_CC=gcc TARGET_PLATFORM=v9 SELECTED_DEBUG=iface > FLEXUS_ROOT=/scratch/kavadias/SimFLEX/flexus-2.1.1 > > in /scratch/kavadias/SimFLEX/flexus-2.1.1/core) > > In order to run ./prepare-test-app I do make uninstall in FLEXUS_ROOT > and then make install again before running ./create-initial-flexpoint > TraceFlex which crashes > as described above. > > Does someone understand where is the problem? Can anyone please help me with > this?? > If not, is there any sense in trying to aquire a version of simics with > 32-bit libraries from virtutech > and compile flexus with 32-bit libraries as well (maybe the -fPIC flag > exaggerates some bad > behavior?) ??? > > Thanks, > > Stamatis Kavadias > _______________________________________________ > SimFlex mailing list > [email protected] > https://sos.ece.cmu.edu/mailman/listinfo/simflex > SimFlex web page: http://www.ece.cmu.edu/~simflex > From bramad2 at lsu.edu Mon Oct 29 16:39:49 2007 From: bramad2 at lsu.edu (Balachandran Ramadass) List-Post: [email protected] Date: Mon Oct 29 16:39:55 2007 Subject: [Simflex] where did dependency logic implemented. Message-ID: <[email protected]> hi 1.)i am trying to identify the number of dependency insctruction for each load instruction in load store queue. please tell me in which file or which function dependency logic is implemented inside uArch directory for out of order simulation. 2) where did the branch predection logic implemented . I need to check the branch prediction feed back for the branch instruction. Thanking you Bala Louisiana state university
