Hi
I've come across a (rather detailed) problem with the H316 simulation.
The issue is that the current code assumes that the X register always
tracks location zero, but there is a situation where this is not so. On
a machine with more than 16Kwords of RAM, and therefore equipped with
the extended addressing option, if the machine is *not* in extended
addressing mode, and the current instruction is in the upper half of RAM
then the X register actually tracks location '040000 - the first word of
the upper half.
The attached patch file corrects the issue. Note that this patch file is
relative to the code in h316_cpu.c on the "Interim Corrections" page:
http://simh.trailing-edge.com/interim.html
Once patched, simh will cleanly run the main CPU Verification and Test
program, AB16-CCT4, which may be downloaded from here:
http://www.series16.adrianwise.co.uk/software/source/VT/AB16-CCT4/AB16-CCT4_slst.ptp
The attached "do" file, boot_AB16-CCT4 will run it. (The test of the
front-panel sense switches is skipped, and an instruction not
implemented by simh has to be ignored.)
Adrian
--
Adrian Wise
http://www.series16.adrianwise.co.uk
diff -C5 -r tmp/H316/h316_cpu.c H316/h316_cpu.c
*** tmp/H316/h316_cpu.c Wed Nov 16 19:26:56 2011
--- H316/h316_cpu.c Wed Nov 16 19:42:56 2011
***************
*** 233,242 ****
--- 233,243 ----
uint16 M[MAXMEMSIZE] = { 0 }; /* memory */
int32 saved_AR = 0; /* A register */
int32 saved_BR = 0; /* B register */
int32 saved_XR = 0; /* X register */
int32 PC = 0; /* P register */
+ int32 XR = 0; /* X register */
int32 C = 0; /* C register */
int32 ext = 0; /* extend mode */
int32 pme = 0; /* prev mode extend */
int32 extoff_pending = 0; /* extend off pending
*/
int32 dp = 0; /* double mode */
***************
*** 300,310 ****
REG cpu_reg[] = {
{ ORDATA (P, PC, 15) },
{ ORDATA (A, saved_AR, 16) },
{ ORDATA (B, saved_BR, 16) },
! { ORDATA (X, XR, 16) },
{ ORDATA (SC, sc, 16) },
{ FLDATA (C, C, 0) },
{ FLDATA (EXT, ext, 0) },
{ FLDATA (PME, pme, 0) },
{ FLDATA (EXT_OFF, extoff_pending, 0) },
--- 301,311 ----
REG cpu_reg[] = {
{ ORDATA (P, PC, 15) },
{ ORDATA (A, saved_AR, 16) },
{ ORDATA (B, saved_BR, 16) },
! { ORDATA (X, saved_XR, 16) },
{ ORDATA (SC, sc, 16) },
{ FLDATA (C, C, 0) },
{ FLDATA (EXT, ext, 0) },
{ FLDATA (PME, pme, 0) },
{ FLDATA (EXT_OFF, extoff_pending, 0) },
***************
*** 621,631 ****
break;
case 035: case 075: /* LDX */
if (reason = Ea (MB & ~IDX, &Y)) /* eff addr */
break;
! XR = Read (Y); /* load XR */
break;
case 016: case 036: case 056: case 076: /* MPY */
if (cpu_unit.flags & UNIT_HSA) { /* installed? */
if (reason = Ea (MB, &Y)) /* eff addr */
--- 622,632 ----
break;
case 035: case 075: /* LDX */
if (reason = Ea (MB & ~IDX, &Y)) /* eff addr */
break;
! Write((ext)?0:(PC & 040000), Read (Y)); /* load XR */
break;
case 016: case 036: case 056: case 076: /* MPY */
if (cpu_unit.flags & UNIT_HSA) { /* installed? */
if (reason = Ea (MB, &Y)) /* eff addr */
***************
*** 1048,1057 ****
--- 1049,1061 ----
void Write (int32 addr, int32 val)
{
if (((addr == 0) || (addr >= 020)) && MEM_ADDR_OK (addr))
M[addr] = val;
+ if (((ext) && (addr == 0)) ||
+ ((!ext) && (addr == (PC & 040000))))
+ XR = val;
return;
}
/* Add */
***************
*** 1294,1306 ****
{
int32 d;
if (addr >= MEMSIZE)
return SCPE_NXM;
! if (addr == 0)
! d = saved_XR;
! else d = M[addr];
if (vptr != NULL)
*vptr = d & DMASK;
return SCPE_OK;
}
--- 1298,1308 ----
{
int32 d;
if (addr >= MEMSIZE)
return SCPE_NXM;
! d = M[addr];
if (vptr != NULL)
*vptr = d & DMASK;
return SCPE_OK;
}
***************
*** 1310,1320 ****
{
if (addr >= MEMSIZE)
return SCPE_NXM;
if (addr == 0)
saved_XR = val & DMASK;
! else M[addr] = val & DMASK;
return SCPE_OK;
}
/* Option processors */
--- 1312,1322 ----
{
if (addr >= MEMSIZE)
return SCPE_NXM;
if (addr == 0)
saved_XR = val & DMASK;
! M[addr] = val & DMASK;
return SCPE_OK;
}
/* Option processors */
diff -C5 -r tmp/H316/h316_defs.h H316/h316_defs.h
*** tmp/H316/h316_defs.h Fri Nov 21 19:07:52 2008
--- H316/h316_defs.h Wed Nov 16 19:27:18 2011
***************
*** 58,68 ****
#define SIGN 0100000 /* sign */
#define DP_SIGN 010000000000
#define DMASK 0177777 /* data mask */
#define MMASK (DMASK & ~SIGN) /* magnitude mask */
- #define XR M[0]
#define M_CLK 061 /* clock location */
#define M_RSTINT 062 /* restrict int */
#define M_INT 063 /* int location */
/* CPU options */
--- 58,67 ----
set cpu oct
attach ptr AB16-CCT4_slst.ptp
; load the SLST
b ptr
; Kill the sense-switch test
d 001551 103546
; Ignore undefined instruction (a priority interrupt option SMK)
d cpu stop_inst 0
; Run the test
run 1000
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