On Monday, January 4, 2016 at 12:06 PM, Paul Koning wrote: > > On Jan 4, 2016, at 2:53 PM, Mark Pizzolato <[email protected]> wrote: > > > >> ... > > > > I vaguely remember that something else depends on how it is currently > > implemented. The wait delay was added to accommodate the fact that > > something didn't expect immediate response. A delay of 1 is essentially the > > same as no delay. > > > > It is hard to imagine that the OS driver would expect that the device would > > complete some operation in one instruction time. This would tend to fail as > > newer models of CPU were implemented which used the same peripheral > > hardware, no? > > All I can say is that it does work on real hardware. > > The manual says that the bit is "self-clearing". That isn't the same words as > the more common "write only" but it implies roughly the same thing. The > driver definitely does not expect the whole master clear process to complete > in a few instruction times; it patiently waits for RUN to become set. But it > DOES expect that MCLR does not read back as set, not even very quickly > after it was set by the driver. > > So maybe the thing to do is have the process master clear action be started > at the CSR write rather than delayed (while other CSR operations can remain > delayed) so that at least the clear_master_clear part is done right away.
Sounds reasonable. I've got to see if I can find the reason the delay was initially added and make sure a change like this is compatible. > >> By the way, if I connect a DMC to a DMR, it doesn't come up. Is that > >> expected? I thought DMC and DMR were sufficiently compatible that it > >> would work... > > > > They absolutely should work as long as the both get turned on by software. > > The wire protocol is the same. The wire protocol is also compatible to host > > based DDCMP protocol implementations on the PDP10 and RSX since it can > > reliably talk to KMC/DUP configurations. > > Ok, that's what I figured. The wire protocols in the real hardware are > actually > not identical (DDCMP 3.1 vs. DDCMP 4.0, and in the case of the "high speed" > DMC-11, 3.1 with some bugs that I might still have documented somewhere). > But yes, they are supposed to be interoperable. I still need a RSTS disk image and configuration file which has several DMC/DMR's configured and attempts to start the network.... Thanks. - Mark _______________________________________________ Simh mailing list [email protected] http://mailman.trailing-edge.com/mailman/listinfo/simh
