The VAX architecture went through several major emendations - including
both extensions and removals - from its initial version in the late 70s
until it was "frozen" in 1990.
The architecture always deliberately excluded a couple of areas, in
particular, IO, error handling, and the console. All of those were
system specific.
The original VAX architecture specification was unveiled with the 11/780
in late 1977. It included the "standard" instruction set and PDP11
compatibility mode. It was amended, almost immediately, to include
interlocked queues and G-floating and H-floating as part of the
"standard" instructions. G- and H-floating were an attempt, futile as it
turned out, to get VAX format adopted for the IEEE floating point
standard by providing extended exponent range and quad precision
floating point.
The next major revision occurred over 1982-1984 as part of the MicroVAX
program. It included two major changes:
- Compatibility mode was made optional and deprecated. It was, in fact,
dropped immediately by the full VAX systems then in the design stage
(8800, 8200), because all compatibility mode software had been removed
from VMS by that point.
- A "MicroVAX subset" was defined. This went through several iterations
around memory management. Eventually, it settled on subsetting just the
instruction set by removing h-floating and octaword, decimal, character
string except MOVC3/5, etc. Floating point was allowed to be optional or
F-/D- only, F-/G- only, or F-/D-/G- only. (MicroVAX I had two variants,
F-/D- and F-/G-, due to control store size constraints. MicroVAX II was
F-/D-/G-.) Certain IPRs were made optional as well, notably TODR.
Eventually, an "rtVAX subset" of memory management was also defined, per
the previous mail discussion of subset memory management.
The tremendous success of MicroVAX II led to further dialog between the
chip designers and the software groups on how the "subset VAX"
definition could be refined to provide adequate performance on all VAX
software. For example, new CRC algorithms employing byte- or word-wide
tables clearly outperformed the CRC instruction's 4b algorithm. The
COBOL group showed that shadowing packed decimal variables in binary
performed as well as microcoded packed decimal. Consequently, in late
1986, the instruction set was restructured into a "core" set, several
"application specific" subsets, and an emulated only set:
- The core set was the MicroVAX II subset, including F-/D-/G- floating,
with the addition of six more string instructions (LOCC, SKPC, SPANC,
SCANC, CMPC3, CMPC5) and the removal of nine floating point instructions
(ACBf, POLYf, EMODf).
- Three application-specific subsets were defined: packed decimal,
extended accuracy (h-floating), and the new vector instruction set.
- The emulated only set was MATCHC, MOVTC, MOVTUC, CRC, EDITPC, ACBf,
EMODf, and POLYf.
As a "swing" design between the original MicroVAX II subset and the new
definition, CVAX implemented the new string instructions and retained
the deprecated floating point instructions. Rigel and NVAX were "core"
only. The vector extension was codified too late for CVAX. It was
implemented by Rigel/Mariah and the VAX9000 but dropped in NVAX due to
lack of market success.
The last revision occurred in 1989 to define support for physical memory
> 1GB (inclusive of IO space). System space (S0) was extended from 1GB
to 2GB - 32B (the reserve was needed because of how the compatibility
exception reported register operands) to allow for larger process page
tables. The PFN was extended from 21b to 25b by gobbling all the
"software reserved" bits in the PTE. This allowed the VAX to support 4GB
of virtual memory and 16GB of physical memory (inclusive of IO space).
With the advent of Alpha, it was felt that larger physical memory
support was not needed. After some back and forth, VMS limited its
support to 4GB (32b) rather than 16GB (34b).
One major change was never implemented: Virtual VAX (1987). This allowed
for virtualization in the VAX architecture, in support of a program
called SeVMS (Secure VMS). It made small changes throughout the
privileged architecture. A prototype was built using the Write Control
Store on the 8800, but no product was ever shipped.
The VVAX proposal also included support for modify faults (faulting on
writes with PTE<m> = 0) as a distinct option. This was implemented in NVAX.
VMS retained instruction compatibility for applications by providing
emulators for all deprecated instructions as well as for all four
formats of floating point (to support the goal of selling uVAX as a
chip). This is determined at runtime, not by CPU model number, so it's
perfectly feasible to have an emulated CVAX with vectors or a 780
without POLYf, which never existed in the real world.
/Bob
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