> On Sep 6, 2018, at 2:32 PM, Timothe Litt <l...@ieee.org> wrote:
>
>
> On 05-Sep-18 22:13, Bob Supnik wrote:
>> Apparently, the GT40 does this. So... problems.
> The KDP (KMC/DUP) and KDZ (KMC/DZ) also do this. Once the KMC11 was
> available, this became a fairly popular method to off-load character
> processing & turn character interrupts into DMA. When I did the KDP
> emulation, Mark & I negotiated a private API rather than emulate NPR to the
> DUP. See pdp11_kmc.c. (In the hardware, the KMC ucode runs the dup (or dz)
> with interrupts disabled & polls the DUP/DZ CSRs often enough to catch
> individual characters. It then DMAs validated messages into memory. The
> polling would have been pretty expensive to emulate.)
>
> I can't speak to whether any Qbus device does DMA to the IO page - off-hand,
> I can't think of a DEC device that would have done that.
>
> It's certainly true that if CPU internal registers were accessible to DMA
> writes, bad things could happen. However, it may not be necessary to fence
> them off in the emulator. In the hardware, I'd expect such
> a device to get a NXM (bus timeout). Or maybe the write is ignored. So
> unless a device exists that expects that behavior, which seems doubtful, the
> issue can probably be ignored. Of course, having said that, there'll
> probably be some diagnostic that tests NPR timeouts that way :-(
>
> (Even more evil would be that some early (unibus) 11's had the GPRs in I/O
> space -- I think an implementation artifact, but it was handy to be able to
> read them directly off the switches for debugging.)
GPRs in the I/O space is, for the most part, something visible only to console
switches, not even the program in the CPU let alone I/O devices. But there is
one famous example, the 11/05, which can execute code from the GPRs. And in
that case, the PC increments by 1 rather than 2 because the GPR addresses are 1
apart rather than 2. This allows very short "is this CPU working" tests on an
11/05 without any functioning memory.
For SIMH, it would be sufficient to make non-CPU I/O space addresses visible to
DMA. But as you said, if, say, the MMU addresses were to answer to DMA
requests, that would probably be ok because existing programs are not going to
do such a thing.
paul
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