On 2018-09-06 22:36, Eric Smith wrote:
On Thu, Sep 6, 2018 at 1:59 PM, Bob Supnik <b...@supnik.org
<mailto:b...@supnik.org>> wrote:
Now, as to bus maps. The 11/70 bus map has a jumper-adjustable upper
limit for what parts of Unibus address space go through the map, and
what parts are resolved on the Unibus itself. The maximum value is
760000; that is, the IO page can never be mapped to memory.
By coincidence I was recently looking over the 11/70 (KB11-C CPU) and
MK11 (semiconductor memory box) documentation. The latter claims that if
you fill an MK11 with the M8722 storage array boards (256KB/128KW each),
to have 4MB/2MW of memory in a single MK11 box, the 11/70 will not work.
I was surprised; I expected that the KB11-C would simply not perform
memory requests for physical addresses in the I/O page, whether those
accesses originated from the CPU or the Unibus. The MK11 docs say that
you have to omit two storage array boards (if using interleaving) or one
board (if not), so the maximum is 3584KB/1792KW interleaved or
3840KB/1920KW non-interleaved, rather than 4088KB/2044KW that would
otherwise be possible.
Hmm. There is a potential side issue problem that might be the reason
for this limitation, and that don't have anything to do with memory as such.
The problem is that the MK11 memory boxes also have CSRs, and those are
living in that last 8K space. If you have memory mapping those same
addresses, I have no idea what happens, but either way is not good.
Either you have the memory, in which case the CSRs are unaccessible, and
they control how the memory box works. Or else you have the CS‰s, but
what then happens to those memory cells?
Johnny
--
Johnny Billquist || "I'm on a bus
|| on a psychedelic trip
email: b...@softjar.se || Reading murder books
pdp is alive! || tryin' to stay hip" - B. Idol
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