On Tuesday, January 1, 2019 at 8:52, Al Kossow wrote:
> Does the simulation support CPU and I/O for a processor new enough to
> run MPE V/E ?
Regrettably, no, although I am certainly interested in extending it to do
so.
> Finding HW documentation of an adequate level for the later machines
> had been difficult to find.
That's the major obstacle. Adding the HP-IB machines to be able to run V/E
would require simulating four new areas:
- New privileged I/O instruction microcode.
- Channel I/O microcode.
- General I/O Channel (GIC) for disc, tape, and printer.
- Asynchronous Data Communications Channel for terminals.
The microcode listing for the dual-ALU Series 64/68 is available but is
difficult to understand because (a) there's no manual describing the
various micro orders, and (b) there's no manual describing the parallel ALU
operation in enough detail to understand the interaction between the two
microcode streams. The I/O instruction and channel microcode is present in
the single-ALU models (Series 39-52), which would be much easier to
understand, but there are no microcode listings available for these models.
Neither of the hardware channel devices are described in enough detail to
simulate them with any confidence. The Series III interfaces had extensive
theories of operation that tied into the supplied schematics. While
schematics of the channels are available, there is only limited discussion
of their operation and no programming-level information at all.
It might be possible to infer all of this from the schematics, dual-ALU
firmware, and the MPE software drivers, but the process would be long,
arduous, and problematic as to success. By way of comparison, it took me
three years of reasonably continuous work to write the Series III
simulator, and that was starting with a full set of detailed hardware and
microcode manuals, plus hardware-level diagnostics.
-- Dave
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