Thanks, Bob. This was a very interesting read.
I have some question. Regarding physical address space - do you really
think that it would have made sense to expand it further? It would have
forced adding a mapping scheme similar to the Unibus map also for the
Qbus, and probably reworking the Unibus map as well, I assume. While
obviously doable, was there that much of a need to expand beyond 4MB
that it was worth such a change? And was there willingness to change the
operating systems in this way? It could have been problematic with the
parts that are closely coupled with the MMU, even at a user level
application. (Obviously, today I'm running on my machines more or less
alone, and then 4MB is more than plenty, and I remember in the mid 80s
running 40-50 people on an 11/70 being rather painful... But still, a
change in this area would not have been that straight forward, I believe.)
Also, RSX, for example, have provisions for 512 byte alignment of pages
instead of the 64 byte alignment. If the PARs would have been redefined
for that, you could have freed 3 bits for physical addresses as well,
instead of working something into the PDR register. Was this ever
considered, or where did RSX get that idea from?
And I know (well, guess/assume/think I saw it hinted) that at least one
mP system was made internal at DEC, based on the J11, but was there ever
any actual plans to make any commercial mP systems based on the J11?
Finally, I know it has been talked about in the past that the target
speed of the J11 was 20MHz (which I think would lead to the 5MHz
instruction frequency) was the target, but it was essentially never
reached. Do you know anything more about that bit? And what about
getting it to run faster? People certainly wanted faster machines...
Johnny
On 2020-07-11 20:09, Bob Supnik wrote:
The J11 was started in mid 1979, in the subsection of Small Systems
Engineering (the low-end PDP11 group) that handled microprocessor
design. In the prior six months, I had been working as a systems
analyst/product strategist in SSE and moonlighting as a microprogrammer
on the F11 CIS option. I wrote a strategy paper recommending two
projects: a 32b VLSI VAX and one last PDP11 microprocessor. Both
recommendations were accepted. The 32b VLSI project was Scorpio (V11),
and the PDP11 project was J11.
J11 was intended to converge the three different lines of PDP11
development that had emerged in the early and mid 70s:
- Low end systems (11/05 -> LSI11 -> F11)
- Mid range systems (11/40 -> 11/34 -> 11/44)
- High end systems (11/45 -> 11/70)
It would be the logical successor to the LSI11 and F11 in the Qbus board
and systems space, but it would have the performance and features of the
high-end processors, including the never-shipped MPs.
This led to the basic requirements:
- 11/70 feature set (two general register sets, three modes, PIRQ, cache
support, I and D space), plus more recent add-ons, like CSM and
interlocking ASRB.
- 11/70 class performance, by running at 5Mhz (200ns cycle time).
- Integral and accelerated floating point.
- CIS option.
Some features were dropped, like the trapping (as opposed to faulting)
memory management modes; they were not used by RSTS/E or RSX11M+. And an
opportunity was missed: to use bits in the PDR to increase physical
memory space beyond 4MB.
By the time J11 finally shipped in 1983, the "all-in on VAX" strategy,
promulgated by Gordon Bell before he left, was in full swing, and
further technology investments in PDP11 CPUs were discouraged.
Accordingly, the CIS option was dropped, as was any thought of a
successor product. Dom LaCava and Jesse Lipcon spun variants on J11
through the end of the 80s and made the PDP11 group one of the most
profitable in DEC. In the 90s, Mentec created a PDP11 CPU (M11) using
off-the-shelf VLSI parts, and then reimplemented it as an ASIC (M1).
A couple of anecdotes:
- In order to have a "CAD forward" strategy, with tools replacing paper
design, I asked Dick Clayton, the responsible VP, for a dedicated KS10
(1/3 of a mip!) for the project. He thought this was totally outrageous
- a dedicated time-sharing system for just one team! - but eventually
authorized the acquisition.
- The Harris team had no experience with high-speed design and some its
issues, such as metastability. The first schematics were filled with
hazards. The chief Harris circuit designer was summoned to Hudson MA,
and Bob Stewart - who had discovered and fixed the metastability issues
in the 11/45 - patiently taught a multi-hour tutorial on metastability
and the need for stacked flip-flops. The Harris designer kept proposing
workarounds, and Bob patiently analyzed the results and showed that the
hazard has simply been moved somewhere else.
- Interconnect verification (IV) on the T11 had taken months of tedious
hand labor, and it was only 17,000 transistor sites. The J11 was much
larger. Accordingly, the J11 team hired a small army of summer students
to create a machine-readable netlist from the paper circuit schematics
and used the KS10 to do computer based IV - a first for DEC.
/Bob Supnik
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