Weddington, Eric wrote:
-----Original Message-----
From:
[email protected]
[mailto:simulavr-devel-bounces+eweddington=cso.atmel....@nongn
u.org] On Behalf Of Joerg Wunsch
Sent: Wednesday, March 11, 2009 3:24 PM
To: [email protected]
Subject: [Simulavr-devel] version bump
I think there needs to be a project list for GSOC.
I definitely agree with you there. It's just this has had so much activity,
what should be put on such a project list for GSoC?
The current TODO is a starting point.
Adding the missing models from the C version is probably
a good GSoC project. Grow it from there to add the CPU
models which are only memory size and peripheral subset
variations. I don't know the effort required though.
I wouldn't expect a student to start cold correcting
an existing CPU model simulation or fixing issues in it.
Knut mentioned a multiple CPUs example that doesn't run.
Probably too little work for GSoC. But important.
I think testing avr-gcc is the next hurdle. But again
that is not a GSoC project.
I think one of you guys needs to write the context
switch code for RTEMS now that there is a simulator that I
can debug the port with. <hint>
--
Joel Sherrill, Ph.D. Director of Research & Development
[email protected] On-Line Applications Research
Ask me about RTEMS: a free RTOS Huntsville AL 35805
Support Available (256) 722-9985
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