Hi,
thanks for this message. Problem is, that on at90can processors (all,
not only 128) the assignment of interrupts is wrong. (here, in special
interrupt 7 is assigned twice, but the message is a little bit "mysterios")
Could you create a bugreport on
http://savannah.nongnu.org/bugs/?group=simulavr? So, this problem can be
tracked.
cu, Thomas
Am 26.07.2012 20:56, schrieb Ytai Ben-tsvi:
Hi!
I've built simulavr from source on Ubuntu / 64-bit.
I'm getting:
$ simulavr -d at90can128 --gdbserver
simulavr: irqsystem.cpp:289: void
HWIrqSystem::DebugVerifyInterruptVector(unsigned int, const Hardware*):
Assertion `existing == source' failed.
Aborted
I'm getting the same behavior with the pre-built binaries.
It works OK with other targets (e.g. atmega 8).
Any ideas?
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