From: Tomoya MORINAGA <[email protected]> Date: Mon, 13 Dec 2010 15:24:09 +0900
> there is endianness issue both Tx and Rx. > Currently, data is set like below. > Register: > MSB--LSB > x x D0 D1 > x x D2 D3 > x x D4 D5 > x x D6 D7 > > But Data to be sent must be set like below. > Register: > MSB--LSB > x x D1 D0 > x x D3 D2 > x x D5 D4 > x x D7 D6 (x means reserved area.) > > Signed-off-by: Tomoya MORINAGA <[email protected]> Applied. _______________________________________________ Socketcan-core mailing list [email protected] https://lists.berlios.de/mailman/listinfo/socketcan-core
