Hi All,
Here is some information about the Xilinx FPGA on the net6501.
I managed to program it by using the onboard JTAG port which is JP10.
Here is the pinout of JP10:
o
GND X X VCC (FPGA P26)
GND X X TMS (FPGA P1)
GND X X TCK (FPGA P76)
GND X X TDO (FPGA P75)
GND X X TDI (FPGA P2)
Here are some interesting pins on the FPGA:
- P50 --> red "error" led (D10)
- P52 --> green "ready" led (D8)
- P43 --> clock
The chip model is XC3S50A-VQG100, documentation can be found at
the following URL:
http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf
I made a small "hello world" demo video:
http://www.youtube.com/watch?v=U-ceqqvuZWo
I used a UrJTAG with a BusBlaster board
(http://dangerousprototypes.com/docs/Bus_Blaster).
Here are some UrJTAG session logs:
jtag> cable JTAGkey
Connected to libftd2xx driver.
jtag> detect
IR length: 6
Chain length: 1
Device Id: 00000010001000010000000010010011 (0x02210093)
Manufacturer: Xilinx (0x093)
Part(0): xc3s50a (0x2210)
Stepping: 0
Filename: /usr/share/urjtag/xilinx/xc3s50a/xc3s50a
# --> this is a copy of the xc3s50a_vq100 file
jtag>
jtag> svf fpga/fpga.svf stop progress
detail: Parsing 960/967 ( 99%)detail:
detail: Scanned device output matched expected TDO values.
jtag>
jtag> instruction EXTEST
jtag> shift ir
jtag> set signal IO_P50 out 1 # turn red off
jtag> set signal IO_P52 out 1 # turn green off
jtag> shift dr
jtag> set signal IO_P50 out 0 # turn red on
jtag> set signal IO_P52 out 0 # turn green on
jtag> shift dr
jtag>
Interesting fact, the "Reset" button located next to the power connector
becomes unresponsive after reconfiguration of the FPGA ...
William
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