{74HC4060 CMOS OSC/14 stage binary divider}
I am confident that we might have stumbled upon some approaches to designing pll controled vfo's for SDR if we look at reducing the matters of thermal drift for one thing which causes the pll to make step corrections more often. The slower the drift the less the pll will need to correct the vfo. Hence it will not be jumping steps allot. I would not consider this a problem for use with broadcast and voice communications however if you are receiving digital communications of the very narrow bandwidth type or are using something like Jason then the vfo needs to be as stable as can be.
I noticed that some of the approaches to the various designs were stretching the designs too far in complexity. I decided on the Slow Tune Fast Stabiliser since it starts off with a pll VCO chip that contains a CMOS OSC section and a binary dividable counter section. This is similar to the way CB pll chips work however this is made for more than just a single band of frequencies such as the CB has. Similar to the CB pll chip is the idea of the dividable counter using selection steps that are binary in nature. The pins however do not change the binary output but are themselve selectable outputs. So there are numerous outputs that are running at the same time. Some of these other pins with signals based upon the vfo may come to be used in time for signals to other things. What sort of things? I do not know since they do change with the change in vfo frequency on the dial.
What I might use the extra outputs for are to derive the vfo output signal from which is considerably divided down in binary steps. Binary divisions go like this, 1,2,4,8,16,32,54,128,etc. If the vfo tunes across 1 MHz and you divide it into two then it tunes across 500 KHz of bandwidth and the noise bandwidth is also cut in half. Actually the circuitry itself may add noise and so the noise "bandwidth" might not look like it was cut in half. It however will be less and so will the period or rate of jitter. In turn if we divide the frequency four times then the tuning will not cover 250 KHz and the noise of the vfo is now 1/4 as wide as it was and 1/4 the frequency it once was.
Notice that this does not get rid of the noise in dB terms but merely reduces the bandwidth which can help out in communications. Wide bandwidth noise will mask the weak signals up and down the band.
I have ordered a Soft Rock 40 which will give me an immediate circuit to construct and get me going on exploring the use of the Huff & Puff stablizer with. So I will start off this way, and as I go along I will try some of my own Mosfet circuit designs I have in mind for the Quadrature detector.
I am getting the V6 for 40/80 meters so I can use the 3 MHz range as an i.f. and I will mix things down into a single i.f. at 3 MHz. This is also within range of my main receiver i.f. and so when I am done I will place it in my receiver and there it will stay.
One final thing, I have found a thermal heating circuit of a simple type used to preheat and maintain a constant temp inside a vfo cabinet. It is described in the ARRL 2005 HB. Basically it is a VFO oven and when coupled with the simple thermal drift compensation network I found there also, it perhaps can give you something ultimate if you want to be a designer that takes ideas real far for personal use.
Basically you raise the temp a few degrees and keep it there. Thermisters and resistors are part of the main features and a simple control circuit which I seem to recall is of IC contruction.
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