--- In [email protected], "iami78" <[EMAIL PROTECTED]> wrote: > > > Cheers everyone! > > First of all, what a GREAT group this is. This is my first post > here. > > I've been building IQ transceiver, pretty much based on Gerald > Youngblood's design. Now I have a small problem: > > I have reserved two AD9954 for the IQ vfo. My original plan was > sync them BUT, I've heard that AD9954 can be used with even as high > as 500MHz external reference clock. Is this true? In that case it is > true, what can I expect from the max. output frequency? > > It just came to my mind, that I might also use just one AD9954 with > 74ALVC74 or equivalent divider to form IQ vfo. My goal is to have > 0-52MHz (160m to 6m) transceiver, so 52MHz*4 = 208 MHz is required > from a single AD9954. Is this possible? > > 73 de Janne, OH1GTF
Hello Janne, welcome to the group which, I am sure, will benefit from any contribution you will give. The AD9954 should have the same core of the AD9951. This latter has been used by Giuliano I0CG in his SDR-X receiver, with a clock of 500 MHz. The SDR-X can receive up to the 6m band, so the DDS must be able to generate at least up to 51 * 4 = 204 MHz, and actually it is. At that frequency there are much more spurs than at lower frequencies, but in any case the spurs level is lower than in the much celebrated SDR-1000. Giuliano told me that it tested the AD9951 even at 600 MHz clock frequency, and it continued to work, though it is spec'ed only up to 400 MHz. Good luck with your project. 73 Alberto I2PHD
