--- In [email protected], "WB6TPU" <[EMAIL PROTECTED]> wrote: > DDS spurs are an entirely different topic and are primarily generated > due to the following mechanisms: clock spur feedthru, numerical > truncation errors in the phase accumulator, angle to amplitude mapping > errors and imperfections in the DAC.
Hello Yes, you right. Simple google with "dds phase dithering" some tech topics for reading http://www.ieee.li/pdf/essay_dds.pdf http://www.microswiss.ch/tld/2003/papers/Wattinger.pdf http://www.freepatentsonline.com/20070040615.pdf latest AD DDS support this feature. FPGA vendors xilinx and actel support this feature also some time ago I working on modeling phase dithering and have some results. my model is the dds with 16bit accumulator, 8bit sin table address space. here http://forum.cqham.ru/download.php?id=22651 you can see spectrum without phase dithering/ max spur have -48dB amplitude phase dithering wit 5bit noise component http://forum.cqham.ru/download.php?id=22650 phase dithering wit 7bit noise component http://forum.cqham.ru/download.php?id=22649 phase dithering wit 8bit noise component http://forum.cqham.ru/download.php?id=22648 as result we have max spur at level -70dB and 22dB improvement PS sorry my english
