About RF Ripple Reduction
The Digital VFO LTspice file I uploaded yesterday, can have its VCO
leakage signal that makes it through into the VFO tank circuit in the
nano volt range, filtered from RF ripple by merely adding a 1K
resistor from the line at the end of the VFO tank to the Noise Test
Point, to the ground. This then will filter off the RF ripple on the
VCO waveform that leaks down into the VFO tank resonance circuit.
As far as this small level VCO signal squarewave entering into the
VFO tank goes. Since it is a product of the VFO signal and the clock
reference in a mixed signal version. It is not altogether desirable
to try and reduce it down in amplitude and try to eliminate it from
the tank circuit. Since it acts as a low level excitation energy that
is synced with the VFO and clock. You want a little bit of that
signal in the VFO circuit itself but not enough to add unwanted noise
and amplitude after amplified in the VFO amps. Hence it is desirable
in a subliminal signal way. Since it is a product of the clock and
the VFO itself.
The truth is that no matter what you do, you could not rid this
small leakage signal from entering into the VFO not matter what you tried.
Although the RF ripple on the VCO leakage signal is small as you can
see in the file, I thought I would tell you a simple method for
ridding it altogether. Just add that 1K resistor at the end of the
VFO tank to ground. And then look at the Transient Analysis of the
VFO at the Noise Test Point. Compare the before and after snap shots
of the squarewave.
Although the VCO control voltage is to change the Varactor diode
capacitance. The small nano volt level VCO leakage current acts as a
low level sync pulse in the VFO circuit itself.
Removal of the unwanted RF ripple energy might make for a better
byproduct free VFO. Since the higher frequency clock signal could mix
into the VFO and produce a unwanted product.
Remember that it is not the squarewave signal that controls the
Varactor but the charge that the squarewave signal delivers to the
charge pump capacitors that reverse biases the varicap diode.
The low noise levels ought to interest some of you. The VCO
leakage signal is on the order of 800~900 nana volts (0.9mV) and the
noise is on the order of 4.4nV/Hz*1/2.
Harmonics start off at -190 dB and by 1 MHz are down to -260 dB.
And all higher harmonics are below this. So, spurious byproducts are
virtually non existent in this circuit. Thanks to the heavy Lock Loop
capacitance in the charge pump.
My Incremental Tuning Discovery:
Last year while working around on the test bench with a working
model of this circuit, I discovered a incremental tuning modification
that involves modifying the waveform into a saw wave. You can do this
by changing the 10pF capacitor in the Lock Loop Filter between the two
25k resistors to 1000pF. Run the Transient Analysis.
The 74HC74 gravitates around the midpoint amplitude of the leading
edge of the compared waveforms. The saw wave form now gives the
74HC74 more of a duration period upon the leading edge which is now
almost sinewave like, and hence it can search for a lock point
somewheres over this wider leading edge to lock onto. And this means
that the output amplitude is now variable and is not fixed as in the
case of the squarewave. Hence amplitude variations give the circuit
more control on the incremental between lock step frequency points.
The longer the circuit lingers around on the wider duration of the saw
wave leading edge before it locks. The higher the output amplitude
is. This adds more dynamic range to the VCO control voltage.
Charge build up is slowed down when the amplitude is steady, because
the duration of the peak of the saw waveform is smaller, but the
abilty to have variations in amplitude can make quicker changes.
In the working circuit I noticed that the circuit seemed to have a
mind of its own when I did this. If it needed to produce a square
wave, it could still do that. And although LTspice will not run it, I
could use a 10uF capacitor across the 74HC74 output and do this. And
this was with the working model on the test bench so I know that I can
use a larger capacitor and it still works.
This cirucit has a lot of future potential as of yet unrealized.
But if it is not built right, and is not based upon a root circuit
concept. It is not of much use to try and develop. The Huff and Puff
files do not have much in terms of insight or circuit explanations or
theory. Hence they lack fundamental views and concepts and even lack
a common circuit configuration or root circuit from which limbs can be
added onto to modify and improve the idea.
After some looking over the ideas, the root circuit configuration is
the one I have in my circuit diagram. Regardless of whether you are
using a HF crystal oscillator or a VLF tuning fork watch crystal for
the clock reference (time base).
And the former practice of leaving the unused complimentary output
unloaded in a Flip Flop section that is used in the chip, Is an idea
that upsets the internal balance of the current in the two halves of
the outputs and upsets the trigger point at the mid amplitude region
of the leading edge. The circuit works while unloaded like this,
though it works better with proper loading of both outputs regardless
of whether the other output signal is used.
Dan
