The Digital VFO LTspice file has had a few small improvements made and a few notes on the scope of the improvements. A few added graphics are included.
Revised file is here: http://groups.yahoo.com/group/soft_radio/files/SDR%20Spice%20Analysis%20Files/Huff_And_Puff.zip A better output port balance, better filtering due to such, as well as the 1k ohm VCO RF ripple filter have been added to the circuit. Some small passing discussion of the idea of the math used with the 74HC4060 binary counter (divider) stage and the frequency steps that the circuit locks up on are included for a little insight. I could have commented allot on this aspect but I didn't, that would have been a volume. This file revision is for the purpose of making the transition point of the edge triggering, more precise through proper loading of the outputs of the Comparator chip section. Actually it is all simple. In circuit modification terms. Remember that you can make adjustments in a real test bench circuit to get the circuit to work with your Varactor diode load and the load of the VFO tank. You can increase or decrease the charge pump capacitors for different time constants, etc. And so some tweaking of the model you build can be done if needed to start up the circuit. But it does not have much trouble as far as I have experienced. I has no trouble starting up at all, you have to check that it is locking mostly. You can also model the circuit you modified with this LTspice file by adding in the parts values you have used on the test bench. What you can't see in the scope or frequency counter you might see in the Spice file. Dan
