--- In [email protected], "Patricia Wilson" <[EMAIL PROTECTED]> wrote: > > Thank you Carlos, a useful answer. > > I am rather new to this SDR thing and have a really newby question. > Where in the chain between antenna and speaker should the signal be > sampled by an SDR? The Nyquist limit imposes a sample rate of at > least twice the highest frequency component so if you want to sample > at the input RF and that RF is 29 MHz then you need a sample rate of > 58 MHz which is not only pretty fast but will also produce a LOT of > data very quickly. On the other hand if you mix it down to a first > IF you lose the possibility of digitally filtering out unwanted > signals earlier in the signal path before they have a chance to > overload something. > > As with nearly everything in engineering it is a trade-off. But > where do most SDR's do the sampling?
Patricia, I am Alberto, not Carlos. There are two main courses in the SDR schools of thought, each addressing different needs. The simpler, less expensive, though giving good results method is that called "the Tayloe mixer". The name Tayloe is a bit misleading, as he did not invent that mixer architecture, but despite prior art he was able to obtain a patent from the US Patent Office, notorious for its sloppiness... A SDR based on that mixer architecture, more aptly called QSD (Quadrature Sampling Detector) uses a local oscillator with two outputs at 90 degrees from each other that feed the mixer. The LO frequency is equal to the center frequency of the band segment to be received. Practically a zero IF. The output of the mixer is a couple of signals in baseband, called I and Q, which analytically describe the band of interest. Those signals are then sent to the stereo inputs of a good quality sound card, and digitized by the A2D converters on that board. The sampling frequency used on the sound card determines (in addition to the hardware filtering in the mixer) the max bandwidth receivable. Good sound cards can sample up to 192 kHz, and this means that you have just a bit less than 192 kHz of bandwidth. Nyquist is still happy, as you work with an analytic signal (the I/Q pair). Then the software can use the digitized signals for its tasks, like demodulation and filtering. The second school of thought is that that places an A2D converter directly behind the antenna, working at 66 MHz (the SDR-14 and the SDR-IQ), or 80 MHz (the Perseus), or higher (the upcoming Qs1r and Mercury receivers). Of course such a high sampling rate is not directly manageable by a PC, so on the same board of the ADC you will find a DDC (Digital Down Converter) either implemented using commercial chips (e.g. the AD6620 used on the SDR-14 and SDR-IQ boards), or an FPGA with a custom code. Depending on what has been programmed on the FPGA you will obtain a downsampled signal (with the inherent processing gain caused by the downsampling) that can range from a few kHz to a few MHz of sampling rate. The downsampling process is done using a quadrature NCO in the DDC, and the result is again an I/Q pair. Now the data are already digital, and you neednot / cannot use the sound card to bring them into the PC. Generaly what is used is a high speed USB 2.0 port, though the use of the Ethernet port is emerging, thanks to a new product of RFspace, the SDR-IP. While a sampling rate of 1 MHz can look high, modern dual core CPUs can cope quite easily with such a high data rate. As an example, I have an Athlon 64 X2 4500+, and Winrad, when used with Perseus sending data at 1MHz (that means 6 MB/sec of data, as we have a pair of I/Q samples, each 24 bits), uses about 35% of the available CPU to do its tasks of filtering and demodulation. So there is ample romm for higher sampling rates. Hope to have explained in clear terms the status of the art about SDR architectures. 73 Alberto I2PHD
