Module Name: src
Committed By: skrll
Date: Sat May 18 08:49:24 UTC 2019
Modified Files:
src/sys/arch/arm/broadcom: bcm53xx_reg.h
src/sys/arch/arm/omap: omap2_reg.h
src/sys/arch/evbarm/bcm53xx: bcm53xx_machdep.c platform.h
src/sys/arch/evbarm/beagle: beagle_machdep.c
src/sys/arch/evbarm/conf: ARMADILLO-IOT-G3 BEAGLEBONE IGEPV2 N900
OMAP5EVM PANDABOARD VTC100 mk.beagle mk.gumstix mk.imx7 mk.kobo
mk.nitrogen6 std.bcm53xx std.beagle std.gumstix std.imx7 std.kobo
std.nitrogen6 std.overo
src/sys/arch/evbarm/gumstix: gumstix_machdep.c gumstix_start.S
gumstixreg.h
src/sys/arch/evbarm/imx7: imx7_machdep.c
src/sys/arch/evbarm/kobo: kobo_machdep.c
src/sys/arch/evbarm/netwalker: netwalker_start.S
Removed Files:
src/sys/arch/arm/cortex: a9_mpsubr.S
src/sys/arch/evbarm/bcm53xx: bcm53xx_start.S
src/sys/arch/evbarm/beagle: beagle_start.S genassym.cf
src/sys/arch/evbarm/imx7: genassym.cf imx7_start.S
src/sys/arch/evbarm/kobo: kobo_start.S
Log Message:
Convert remaining armv7 kernels to generic start and remove a bunch of
code including a9_mpsubr.S.
Thanks to Lwazi Dube for testing PANDABOARD and BEAGLEBONE.
To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/arm/broadcom/bcm53xx_reg.h
cvs rdiff -u -r1.58 -r0 src/sys/arch/arm/cortex/a9_mpsubr.S
cvs rdiff -u -r1.34 -r1.35 src/sys/arch/arm/omap/omap2_reg.h
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/evbarm/bcm53xx/bcm53xx_machdep.c
cvs rdiff -u -r1.13 -r0 src/sys/arch/evbarm/bcm53xx/bcm53xx_start.S
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/evbarm/bcm53xx/platform.h
cvs rdiff -u -r1.76 -r1.77 src/sys/arch/evbarm/beagle/beagle_machdep.c
cvs rdiff -u -r1.20 -r0 src/sys/arch/evbarm/beagle/beagle_start.S
cvs rdiff -u -r1.1 -r0 src/sys/arch/evbarm/beagle/genassym.cf
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/evbarm/conf/ARMADILLO-IOT-G3 \
src/sys/arch/evbarm/conf/std.beagle
cvs rdiff -u -r1.47 -r1.48 src/sys/arch/evbarm/conf/BEAGLEBONE
cvs rdiff -u -r1.34 -r1.35 src/sys/arch/evbarm/conf/IGEPV2
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/evbarm/conf/N900
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/evbarm/conf/OMAP5EVM
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/evbarm/conf/PANDABOARD
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/evbarm/conf/VTC100
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/evbarm/conf/mk.beagle
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/evbarm/conf/mk.gumstix
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/evbarm/conf/mk.imx7 \
src/sys/arch/evbarm/conf/mk.kobo
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/evbarm/conf/mk.nitrogen6
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/evbarm/conf/std.bcm53xx
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/evbarm/conf/std.gumstix \
src/sys/arch/evbarm/conf/std.overo
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/evbarm/conf/std.imx7 \
src/sys/arch/evbarm/conf/std.kobo
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/evbarm/conf/std.nitrogen6
cvs rdiff -u -r1.61 -r1.62 src/sys/arch/evbarm/gumstix/gumstix_machdep.c
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/evbarm/gumstix/gumstix_start.S
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/evbarm/gumstix/gumstixreg.h
cvs rdiff -u -r1.1 -r0 src/sys/arch/evbarm/imx7/genassym.cf
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/evbarm/imx7/imx7_machdep.c
cvs rdiff -u -r1.2 -r0 src/sys/arch/evbarm/imx7/imx7_start.S
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/evbarm/kobo/kobo_machdep.c
cvs rdiff -u -r1.1 -r0 src/sys/arch/evbarm/kobo/kobo_start.S
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/evbarm/netwalker/netwalker_start.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/broadcom/bcm53xx_reg.h
diff -u src/sys/arch/arm/broadcom/bcm53xx_reg.h:1.17 src/sys/arch/arm/broadcom/bcm53xx_reg.h:1.18
--- src/sys/arch/arm/broadcom/bcm53xx_reg.h:1.17 Sun Sep 16 09:25:46 2018
+++ src/sys/arch/arm/broadcom/bcm53xx_reg.h Sat May 18 08:49:23 2019
@@ -69,11 +69,15 @@
#define BCM53XX_PCIE2_OWIN_SIZE 0x04000000
#define BCM53XX_PCIE2_OWIN_MAX 0x08000000
+#define BCM53XX_ROM_REGION_PBASE 0xfff00000
+#define BCM53XX_ROM_REGION_SIZE 0x00100000
+
#define BCM53XX_IO_SIZE (BCM53XX_IOREG_SIZE \
+ BCM53XX_ARMCORE_SIZE \
+ BCM53XX_PCIE0_OWIN_SIZE \
+ BCM53XX_PCIE1_OWIN_SIZE \
- + BCM53XX_PCIE2_OWIN_SIZE)
+ + BCM53XX_PCIE2_OWIN_SIZE \
+ + BCM53XX_ROM_REGION_SIZE)
#define BCM53XX_REF_CLK (25*1000*1000)
Index: src/sys/arch/arm/omap/omap2_reg.h
diff -u src/sys/arch/arm/omap/omap2_reg.h:1.34 src/sys/arch/arm/omap/omap2_reg.h:1.35
--- src/sys/arch/arm/omap/omap2_reg.h:1.34 Tue Oct 4 16:03:39 2016
+++ src/sys/arch/arm/omap/omap2_reg.h Sat May 18 08:49:23 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: omap2_reg.h,v 1.34 2016/10/04 16:03:39 kiyohara Exp $ */
+/* $NetBSD: omap2_reg.h,v 1.35 2019/05/18 08:49:23 skrll Exp $ */
/*
* Copyright (c) 2007 Microsoft
@@ -93,6 +93,9 @@
#define OMAP4430_EMIF2_BASE 0x4D000000 /* MemCtrl 1 */
#define OMAP4430_EMIF2_SIZE 0x00100000 /* 4KB padded to 1M */
+#define OMAP4430_DMM_BASE 0x4e000000
+#define OMAP4430_DMM_SIZE 0x02000000 /* 32MB */
+
/* OMAP5 processors */
#define OMAP5430_L4_CORE_BASE 0x4A000000
@@ -876,6 +879,7 @@
* PL310 L2CC (44xx)
*/
#define OMAP4_SCU_BASE 0x48240000
+#define OMAP4_SCU_SIZE 0x00000100
#define OMAP4_L2CC_BASE 0x48242000
#define OMAP4_L2CC_SIZE 0x00001000 /* 4KB */
@@ -885,6 +889,7 @@
/* These also apply to OMAP5 */
#define OMAP4_WUGEN_BASE 0x48281000
+#define OMAP4_WUGEN_SIZE 0x00001000
#define OMAP4_WKG_CONTROL_0 0x00000000
#define OMAP4_WKG_CONTROL_1 0x00000400
#define OMAP4_AUX_CORE_BOOT0 0x00000800
Index: src/sys/arch/evbarm/bcm53xx/bcm53xx_machdep.c
diff -u src/sys/arch/evbarm/bcm53xx/bcm53xx_machdep.c:1.19 src/sys/arch/evbarm/bcm53xx/bcm53xx_machdep.c:1.20
--- src/sys/arch/evbarm/bcm53xx/bcm53xx_machdep.c:1.19 Sat Nov 3 15:02:32 2018
+++ src/sys/arch/evbarm/bcm53xx/bcm53xx_machdep.c Sat May 18 08:49:23 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: bcm53xx_machdep.c,v 1.19 2018/11/03 15:02:32 skrll Exp $ */
+/* $NetBSD: bcm53xx_machdep.c,v 1.20 2019/05/18 08:49:23 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -33,7 +33,7 @@
#define IDM_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bcm53xx_machdep.c,v 1.19 2018/11/03 15:02:32 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bcm53xx_machdep.c,v 1.20 2019/05/18 08:49:23 skrll Exp $");
#include "opt_arm_debug.h"
#include "opt_console.h"
@@ -100,6 +100,9 @@ static void bcm53xx_system_reset(void);
#define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */
#endif
+void bcm53xx_mpstart(void);
+void bcm53xx_platform_early_putchar(char);
+
#if (NCOM > 0)
static const bus_addr_t comcnaddr = (bus_addr_t)CONADDR;
@@ -159,6 +162,13 @@ static const struct pmap_devmap devmap[]
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
+ {
+ KERNEL_IO_ROM_REGION_VBASE,
+ BCM53XX_ROM_REGION_PBASE, /* 0xfff00000 */
+ BCM53XX_ROM_REGION_SIZE, /* 1MB */
+ VM_PROT_READ|VM_PROT_WRITE,
+ PTE_NOCACHE,
+ },
#if NPCI > 0
{
KERNEL_IO_PCIE0_OWIN_VBASE,
@@ -192,6 +202,71 @@ static const struct boot_physmem bp_firs
.bp_flags = 0,
};
+#define BCM53xx_ROM_CPU_ENTRY 0xffff0400
+
+void
+bcm53xx_mpstart(void)
+{
+#ifdef MULTIPROCESSOR
+ /*
+ * Invalidate all SCU cache tags. That is, for all cores (0-3)
+ */
+ bus_space_write_4(bcm53xx_armcore_bst, bcm53xx_armcore_bsh,
+ ARMCORE_SCU_BASE + SCU_INV_ALL_REG, 0xffff);
+
+ uint32_t diagctl = bus_space_read_4(bcm53xx_armcore_bst,
+ bcm53xx_armcore_bsh, ARMCORE_SCU_BASE + SCU_DIAG_CONTROL);
+ diagctl |= SCU_DIAG_DISABLE_MIGBIT;
+ bus_space_write_4(bcm53xx_armcore_bst, bcm53xx_armcore_bsh,
+ ARMCORE_SCU_BASE + SCU_DIAG_CONTROL, diagctl);
+
+ uint32_t scu_ctl = bus_space_read_4(bcm53xx_armcore_bst,
+ bcm53xx_armcore_bsh, ARMCORE_SCU_BASE + SCU_CTL);
+ scu_ctl |= SCU_CTL_SCU_ENA;
+ bus_space_write_4(bcm53xx_armcore_bst, bcm53xx_armcore_bsh,
+ ARMCORE_SCU_BASE + SCU_CTL, scu_ctl);
+
+ armv7_dcache_wbinv_all();
+
+ const paddr_t mpstart = KERN_VTOPHYS((vaddr_t)cpu_mpstart);
+ bus_space_tag_t bcm53xx_rom_bst = &bcmgen_bs_tag;
+ bus_space_handle_t bcm53xx_rom_entry_bsh;
+
+ int error = bus_space_map(bcm53xx_rom_bst, BCM53xx_ROM_CPU_ENTRY,
+ 4, 0, &bcm53xx_rom_entry_bsh);
+
+ /*
+ * Before we turn on the MMU, let's the other process out of the
+ * SKU ROM but setting the magic LUT address to our own mp_start
+ * routine.
+ */
+ bus_space_write_4(bcm53xx_rom_bst, bcm53xx_rom_entry_bsh, mpstart);
+
+ arm_dsb();
+ __asm __volatile("sev" ::: "memory");
+
+ for (int loop = 0; loop < 16; loop++) {
+ VPRINTF("%u hatched %#x\n", loop, arm_cpu_hatched);
+ if (arm_cpu_hatched == __BITS(arm_cpu_max - 1, 1))
+ break;
+ int timo = 1500000;
+ while (arm_cpu_hatched != __BITS(arm_cpu_max - 1, 1))
+ if (--timo == 0)
+ break;
+ }
+ for (size_t i = 1; i < arm_cpu_max; i++) {
+ if ((arm_cpu_hatched & __BIT(i)) == 0) {
+ printf("%s: warning: cpu%zu failed to hatch\n",
+ __func__, i);
+ }
+ }
+
+ VPRINTF(" (%u cpu%s, hatched %#x)",
+ arm_cpu_max, arm_cpu_max ? "s" : "",
+ arm_cpu_hatched);
+#endif /* MULTIPROCESSOR */
+}
+
/*
* u_int initarm(...)
*
@@ -313,8 +388,15 @@ initarm(void *arg)
* If we have more than 256MB of RAM, set aside the first 256MB for
* non-default VM allocations.
*/
- return initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE,
+ u_int sp = initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE,
(bigmem_p ? &bp_first256 : NULL), (bigmem_p ? 1 : 0));
+
+ /*
+ * initarm_common flushes cache if required before AP start
+ */
+ bcm53xx_mpstart();
+
+ return sp;
}
void
Index: src/sys/arch/evbarm/bcm53xx/platform.h
diff -u src/sys/arch/evbarm/bcm53xx/platform.h:1.2 src/sys/arch/evbarm/bcm53xx/platform.h:1.3
--- src/sys/arch/evbarm/bcm53xx/platform.h:1.2 Fri Sep 7 11:53:50 2012
+++ src/sys/arch/evbarm/bcm53xx/platform.h Sat May 18 08:49:23 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: platform.h,v 1.2 2012/09/07 11:53:50 matt Exp $ */
+/* $NetBSD: platform.h,v 1.3 2019/05/18 08:49:23 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -59,6 +59,7 @@
#define KERNEL_IO_PCIE2_OWIN_VBASE (KERNEL_IO_PCIE1_OWIN_VBASE + BCM53XX_PCIE1_OWIN_SIZE)
#define KERNEL_IO_IOREG_VBASE (KERNEL_IO_PCIE2_OWIN_VBASE + BCM53XX_PCIE2_OWIN_SIZE)
#define KERNEL_IO_ARMCORE_VBASE (KERNEL_IO_IOREG_VBASE + BCM53XX_IOREG_SIZE)
-#define KERNEL_IO_END_VBASE (KERNEL_IO_ARMCORE_VBASE + BCM53XX_ARMCORE_SIZE)
+#define KERNEL_IO_ROM_REGION_VBASE (KERNEL_IO_ARMCORE_VBASE + BCM53XX_ARMCORE_SIZE)
+#define KERNEL_IO_END_VBASE (KERNEL_IO_ROM_REGION_VBASE + BCM53XX_ROM_REGION_SIZE)
#endif /* _EVBARM_BCM53XX_PLATFORM_H */
Index: src/sys/arch/evbarm/beagle/beagle_machdep.c
diff -u src/sys/arch/evbarm/beagle/beagle_machdep.c:1.76 src/sys/arch/evbarm/beagle/beagle_machdep.c:1.77
--- src/sys/arch/evbarm/beagle/beagle_machdep.c:1.76 Thu Oct 18 09:01:53 2018
+++ src/sys/arch/evbarm/beagle/beagle_machdep.c Sat May 18 08:49:23 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: beagle_machdep.c,v 1.76 2018/10/18 09:01:53 skrll Exp $ */
+/* $NetBSD: beagle_machdep.c,v 1.77 2019/05/18 08:49:23 skrll Exp $ */
/*
* Machine dependent functions for kernel setup for TI OSK5912 board.
@@ -125,7 +125,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: beagle_machdep.c,v 1.76 2018/10/18 09:01:53 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: beagle_machdep.c,v 1.77 2019/05/18 08:49:23 skrll Exp $");
#include "opt_arm_debug.h"
#include "opt_console.h"
@@ -218,6 +218,12 @@ __KERNEL_RCSID(0, "$NetBSD: beagle_machd
#include <dev/usb/ukbdvar.h>
+#ifdef VERBOSE_INIT_ARM
+#define VPRINTF(...) printf(__VA_ARGS__)
+#else
+#define VPRINTF(...) __nothing
+#endif
+
BootConfig bootconfig; /* Boot config storage */
static char bootargs[MAX_BOOT_STRING];
char *boot_args = NULL;
@@ -243,22 +249,6 @@ int use_fb_console = true;
uint32_t omap5_cnt_frq;
#endif
-#ifdef MULTIPROCESSOR
-
-void beagle_cpu_hatch(struct cpu_info *);
-
-void
-beagle_cpu_hatch(struct cpu_info *ci)
-{
-#if defined(CPU_CORTEXA9)
- a9tmr_init_cpu_clock(ci);
-#elif defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15)
- gtmr_init_cpu_clock(ci);
-#endif
-}
-
-#endif
-
/*
* Macros to translate between physical and virtual for a subset of the
* kernel address space. *Not* for general use.
@@ -266,6 +256,7 @@ beagle_cpu_hatch(struct cpu_info *ci)
#define KERNEL_BASE_PHYS ((paddr_t)KERNEL_BASE_phys)
#define OMAP_L4_CORE_VOFFSET (OMAP_L4_CORE_VBASE - OMAP_L4_CORE_BASE)
+
/* Prototypes */
void consinit(void);
@@ -290,6 +281,10 @@ static psize_t emif_memprobe(void);
static psize_t omap3_memprobe(void);
#endif
+#ifdef MULTIPROCESSOR
+void beagle_cpu_hatch(struct cpu_info *);
+#endif
+
bs_protos(bs_notimpl);
#if NCOM > 0
@@ -297,6 +292,24 @@ bs_protos(bs_notimpl);
#include <dev/ic/comvar.h>
#endif
+static void
+earlyconsputc(dev_t dev, int c)
+{
+ uartputc(c);
+}
+
+static int
+earlyconsgetc(dev_t dev)
+{
+ return 0;
+}
+
+static struct consdev earlycons = {
+ .cn_putc = earlyconsputc,
+ .cn_getc = earlyconsgetc,
+ .cn_pollc = nullcnpollc,
+};
+
/*
* Static device mappings. These peripheral registers are mapped at
* fixed virtual addresses very early in initarm() so that we can use
@@ -421,6 +434,82 @@ static const struct pmap_devmap devmap[]
#undef _A
#undef _S
+#ifdef MULTIPROCESSOR
+
+void
+beagle_cpu_hatch(struct cpu_info *ci)
+{
+#if defined(CPU_CORTEXA9)
+ a9tmr_init_cpu_clock(ci);
+#elif defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15)
+ gtmr_init_cpu_clock(ci);
+#endif
+}
+#endif
+
+static void
+beagle_mpstart(void)
+{
+#if defined(MULTIPROCESSOR)
+ const bus_space_tag_t bst = &omap_bs_tag;
+
+#if defined(CPU_CORTEXA9)
+ const bus_space_handle_t scu_bsh = OMAP4_SCU_BASE
+ + OMAP_L4_PERIPHERAL_VBASE - OMAP_L4_PERIPHERAL_BASE;
+
+ /*
+ * Invalidate all SCU cache tags. That is, for all cores (0-3)
+ */
+ bus_space_write_4(bst, scu_bsh, SCU_INV_ALL_REG, 0xffff);
+
+ uint32_t diagctl = bus_space_read_4(bst, scu_bsh, SCU_DIAG_CONTROL);
+ diagctl |= SCU_DIAG_DISABLE_MIGBIT;
+ bus_space_write_4(bst, scu_bsh, SCU_DIAG_CONTROL, diagctl);
+
+ uint32_t scu_ctl = bus_space_read_4(bst, scu_bsh, SCU_CTL);
+ scu_ctl |= SCU_CTL_SCU_ENA;
+ bus_space_write_4(bst, scu_bsh, SCU_CTL, scu_ctl);
+
+ armv7_dcache_wbinv_all();
+#endif
+ const bus_space_handle_t wugen_bsh = OMAP4_WUGEN_BASE + OMAP_L4_CORE_VOFFSET;
+ const paddr_t mpstart = KERN_VTOPHYS((vaddr_t)cpu_mpstart);
+
+ bus_space_write_4(bst, wugen_bsh, OMAP4_AUX_CORE_BOOT1, mpstart);
+
+ for (size_t i = 1; i < arm_cpu_max; i++) {
+ uint32_t boot = bus_space_read_4(bst, wugen_bsh, OMAP4_AUX_CORE_BOOT0);
+ boot |= __SHIFTIN(0xf, i * 4);
+ bus_space_write_4(bst, wugen_bsh, OMAP4_AUX_CORE_BOOT0, boot);
+ }
+
+
+ arm_dsb();
+ __asm __volatile("sev" ::: "memory");
+
+ for (int loop = 0; loop < 16; loop++) {
+ VPRINTF("%u hatched %#x\n", loop, arm_cpu_hatched);
+ if (arm_cpu_hatched == __BITS(arm_cpu_max - 1, 1))
+ break;
+ int timo = 1500000;
+ while (arm_cpu_hatched != __BITS(arm_cpu_max - 1, 1))
+ if (--timo == 0)
+ break;
+ }
+ for (size_t i = 1; i < arm_cpu_max; i++) {
+ if ((arm_cpu_hatched & __BIT(i)) == 0) {
+ printf("%s: warning: cpu%zu failed to hatch\n",
+ __func__, i);
+ }
+ }
+
+ VPRINTF(" (%u cpu%s, hatched %#x)",
+ arm_cpu_max, arm_cpu_max ? "s" : "",
+ arm_cpu_hatched);
+#endif
+}
+
+
#ifdef DDB
static void
beagle_db_trap(int where)
@@ -438,27 +527,7 @@ beagle_db_trap(int where)
#endif
#ifdef VERBOSE_INIT_ARM
-void beagle_putchar(char c);
-void
-beagle_putchar(char c)
-{
-#if NCOM > 0
- volatile uint32_t *com0addr = (volatile uint32_t *)CONSADDR_VA;
- int timo = 150000;
-
- while ((com0addr[com_lsr] & LSR_TXRDY) == 0) {
- if (--timo == 0)
- break;
- }
-
- com0addr[com_data] = c;
-
- while ((com0addr[com_lsr] & LSR_TXRDY) == 0) {
- if (--timo == 0)
- break;
- }
-#endif
-}
+#define beagle_putchar(c) beagle_platform_early_putchar(c)
void beagle_platform_early_putchar(char);
@@ -510,12 +579,15 @@ initarm(void *arg)
beagle_putchar('d');
#endif
- /*
- * When we enter here, we are using a temporary first level
- * translation table with section entries in it to cover the OBIO
- * peripherals and SDRAM. The temporary first level translation table
- * is at the end of SDRAM.
- */
+ /* Heads up ... Setup the CPU / MMU / TLB functions. */
+ if (set_cpufuncs())
+ panic("cpu not recognized!");
+
+ cn_tab = &earlycons;
+
+ extern char ARM_BOOTSTRAP_LxPT[];
+ pmap_devmap_bootstrap((vaddr_t)ARM_BOOTSTRAP_LxPT, devmap);
+
#if defined(OMAP_3XXX) || defined(TI_DM37XX)
omap3_cpu_clk(); // find our CPU speed.
#endif
@@ -528,15 +600,9 @@ initarm(void *arg)
am335x_sys_clk(TI_AM335X_CTLMOD_BASE + OMAP_L4_CORE_VOFFSET);
am335x_cpu_clk(); // find our CPU speed.
#endif
- /* Heads up ... Setup the CPU / MMU / TLB functions. */
- if (set_cpufuncs())
- panic("cpu not recognized!");
init_clocks();
- /* The console is going to try to map things. Give pmap a devmap. */
- pmap_devmap_register(devmap);
-
if (get_bootconf_option(bootargs, "console",
BOOTOPT_TYPE_STRING, &ptr) && strncmp(ptr, "fb", 2) == 0) {
use_fb_console = true;
@@ -582,19 +648,15 @@ initarm(void *arg)
cpu_reset_address = beagle_reset;
-#ifdef VERBOSE_INIT_ARM
/* Talk to the user */
- printf("\nNetBSD/evbarm (beagle) booting ...\n");
-#endif
+ VPRINTF("\nNetBSD/evbarm (beagle) booting ...\n");
#ifdef BOOT_ARGS
char mi_bootargs[] = BOOT_ARGS;
parse_mi_bootargs(mi_bootargs);
#endif
-#ifdef VERBOSE_INIT_ARM
- printf("initarm: Configuring system ...\n");
-#endif
+ VPRINTF("initarm: Configuring system ...\n");
#if !defined(CPU_CORTEXA8)
printf("initarm: cbar=%#x\n", armreg_cbar_read());
@@ -663,8 +725,16 @@ initarm(void *arg)
db_trap_callback = beagle_db_trap;
- return initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0);
+ u_int sp = initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0);
+
+ /*
+ * initarm_common flushes cache if required before AP start
+ */
+ VPRINTF("mpstart\n");
+ beagle_mpstart();
+
+ return sp;
}
static void
@@ -940,10 +1010,10 @@ emif_memprobe(void)
KASSERT(ebank == 0); // No chip selects on Sitara
#endif
memsize <<= (ebank + ibank + rsize + pagesize + width);
-#ifdef VERBOSE_INIT_ARM
- printf("sdram_config = %#x, memsize = %uMB\n", sdram_config,
+
+ VPRINTF("sdram_config = %#x, memsize = %uMB\n", sdram_config,
(u_int)(memsize >> 20));
-#endif
+
return memsize;
}
#endif
Index: src/sys/arch/evbarm/conf/ARMADILLO-IOT-G3
diff -u src/sys/arch/evbarm/conf/ARMADILLO-IOT-G3:1.17 src/sys/arch/evbarm/conf/ARMADILLO-IOT-G3:1.18
--- src/sys/arch/evbarm/conf/ARMADILLO-IOT-G3:1.17 Fri Apr 26 22:46:03 2019
+++ src/sys/arch/evbarm/conf/ARMADILLO-IOT-G3 Sat May 18 08:49:23 2019
@@ -1,4 +1,4 @@
-# $NetBSD: ARMADILLO-IOT-G3,v 1.17 2019/04/26 22:46:03 sevan Exp $
+# $NetBSD: ARMADILLO-IOT-G3,v 1.18 2019/05/18 08:49:23 skrll Exp $
#
# ARMADILLO-IOT-G3 -- Atmark Techno, Armadillo-IoT G3
#
@@ -158,6 +158,7 @@ options PPP_FILTER # Active filter supp
# Console options. also need IMXUARTCONSOLE
options CONSDEVNAME="\"imxuart\"",CONADDR=0x30a70000,CONSPEED=115200
+options EARLYCONS=imx7
# These options enable verbose messages for several subsystems.
# Warning, these may compile large string tables into the kernel!
Index: src/sys/arch/evbarm/conf/std.beagle
diff -u src/sys/arch/evbarm/conf/std.beagle:1.17 src/sys/arch/evbarm/conf/std.beagle:1.18
--- src/sys/arch/evbarm/conf/std.beagle:1.17 Mon Oct 15 16:54:54 2018
+++ src/sys/arch/evbarm/conf/std.beagle Sat May 18 08:49:23 2019
@@ -1,4 +1,4 @@
-# $NetBSD: std.beagle,v 1.17 2018/10/15 16:54:54 skrll Exp $
+# $NetBSD: std.beagle,v 1.18 2019/05/18 08:49:23 skrll Exp $
#
# standard NetBSD/evbarm for BEAGLEBOARD options
@@ -14,12 +14,14 @@ options ARM_HAS_VBAR
options ARM_INTR_IMPL="<arch/arm/omap/omap2_intr.h>"
options CORTEX_PMC
options FPU_VFP
+options MD_CPU_HATCH=beagle_cpu_hatch
options MODULAR
options MODULAR_DEFAULT_AUTOLOAD
options TPIDRPRW_IS_CURCPU
options __HAVE_CPU_COUNTER
options __HAVE_CPU_UAREA_ALLOC_IDLELWP
options __HAVE_FAST_SOFTINTS # should be in types.h
+options __HAVE_GENERIC_START
options __HAVE_MM_MD_DIRECT_MAPPED_PHYS
makeoptions BOARDMKFRAG="${THISARM}/conf/mk.beagle"
Index: src/sys/arch/evbarm/conf/BEAGLEBONE
diff -u src/sys/arch/evbarm/conf/BEAGLEBONE:1.47 src/sys/arch/evbarm/conf/BEAGLEBONE:1.48
--- src/sys/arch/evbarm/conf/BEAGLEBONE:1.47 Wed Feb 6 11:58:30 2019
+++ src/sys/arch/evbarm/conf/BEAGLEBONE Sat May 18 08:49:23 2019
@@ -1,5 +1,5 @@
#
-# $NetBSD: BEAGLEBONE,v 1.47 2019/02/06 11:58:30 rin Exp $
+# $NetBSD: BEAGLEBONE,v 1.48 2019/05/18 08:49:23 skrll Exp $
#
# BEAGLEBONE -- TI AM335x board Kernel
#
@@ -24,6 +24,9 @@ options DEBUG
makeoptions DEBUG="-g" # compile full symbol table
makeoptions COPY_SYMTAB=1
+#options VERBOSE_INIT_ARM
+#options EARLYCONS=beagle # CONSADDR set below
+
## USB Debugging options
options USB_DEBUG
options EHCI_DEBUG
Index: src/sys/arch/evbarm/conf/IGEPV2
diff -u src/sys/arch/evbarm/conf/IGEPV2:1.34 src/sys/arch/evbarm/conf/IGEPV2:1.35
--- src/sys/arch/evbarm/conf/IGEPV2:1.34 Tue Oct 23 19:58:52 2018
+++ src/sys/arch/evbarm/conf/IGEPV2 Sat May 18 08:49:23 2019
@@ -1,5 +1,5 @@
#
-# $NetBSD: IGEPV2,v 1.34 2018/10/23 19:58:52 jdolecek Exp $
+# $NetBSD: IGEPV2,v 1.35 2019/05/18 08:49:23 skrll Exp $
#
# IGEPv2 -- TI OMAP 3530 Eval Board Kernel
#
@@ -112,7 +112,6 @@ options KTRACE # system call tracing,
options DIAGNOSTIC # internal consistency checks
#options DEBUG
#options PMAP_DEBUG # Enable pmap_debug_level code
-options VERBOSE_INIT_ARM # verbose bootstraping messages
options DDB # in-kernel debugger
options DDB_ONPANIC=1
options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
@@ -120,6 +119,10 @@ options DDB_HISTORY_SIZE=100 # Enable h
makeoptions DEBUG="-g" # compile full symbol table
makeoptions COPY_SYMTAB=1
+options VERBOSE_INIT_ARM # verbose bootstraping messages
+options EARLYCONS=beagle
+options CONSADDR=0x49020000, CONSPEED=115200
+
## USB Debugging options
#options USB_DEBUG
#options OHCI_DEBUG
@@ -209,7 +212,6 @@ iic* at omapiic?
#com0 at obio0 addr 0x4806a000 intr 72 mult 4 # UART1
#com1 at obio0 addr 0x4806c000 intr 73 mult 4 # UART2
com0 at obio2 addr 0x49020000 intr 74 mult 4 # UART3 (console)
-options CONSADDR=0x49020000, CONSPEED=115200
# Operating System Timer
omapmputmr0 at obio2 addr 0x49032000 intr 38 # GP Timer 2
Index: src/sys/arch/evbarm/conf/N900
diff -u src/sys/arch/evbarm/conf/N900:1.30 src/sys/arch/evbarm/conf/N900:1.31
--- src/sys/arch/evbarm/conf/N900:1.30 Tue Oct 23 19:58:52 2018
+++ src/sys/arch/evbarm/conf/N900 Sat May 18 08:49:23 2019
@@ -1,5 +1,5 @@
#
-# $NetBSD: N900,v 1.30 2018/10/23 19:58:52 jdolecek Exp $
+# $NetBSD: N900,v 1.31 2019/05/18 08:49:23 skrll Exp $
#
# N900 -- Nokia N900 Kernel
#
@@ -112,7 +112,6 @@ options DIAGNOSTIC # internal consisten
#options DEBUG
#options LOCKDEBUG # expensive locking checks/support
#options PMAP_DEBUG # Enable pmap_debug_level code
-#options VERBOSE_INIT_ARM # verbose bootstraping messages
options DDB # in-kernel debugger
options DDB_ONPANIC=1
options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
@@ -120,6 +119,11 @@ options DDB_HISTORY_SIZE=100 # Enable h
makeoptions DEBUG="-g" # compile full symbol table
makeoptions COPY_SYMTAB=1
+#options VERBOSE_INIT_ARM # verbose bootstraping messages
+#options EARLYCONS=beagle
+#options CONSADDR=0x49020000, CONSPEED=38400
+#options CONSADDR=0x49020000, CONSPEED=115200
+
## USB Debugging options
#options USB_DEBUG
#options EHCI_DEBUG
@@ -233,8 +237,6 @@ tps65950pm3 at iic0 addr 0x4b
# On-board 16550 UARTs
#com0 at obio2 addr 0x49020000 intr 74 mult 4 # UART3 (console)
-#options CONSADDR=0x49020000, CONSPEED=38400
-#options CONSADDR=0x49020000, CONSPEED=115200
# Operating System Timer
omapmputmr0 at obio2 addr 0x49032000 intr 38 # GP Timer 2
Index: src/sys/arch/evbarm/conf/OMAP5EVM
diff -u src/sys/arch/evbarm/conf/OMAP5EVM:1.15 src/sys/arch/evbarm/conf/OMAP5EVM:1.16
--- src/sys/arch/evbarm/conf/OMAP5EVM:1.15 Tue Oct 23 19:58:52 2018
+++ src/sys/arch/evbarm/conf/OMAP5EVM Sat May 18 08:49:23 2019
@@ -1,5 +1,5 @@
#
-# $NetBSD: OMAP5EVM,v 1.15 2018/10/23 19:58:52 jdolecek Exp $
+# $NetBSD: OMAP5EVM,v 1.16 2019/05/18 08:49:23 skrll Exp $
#
# PANDABOARD -- TI OMAP 4430 Eval Board Kernel
#
@@ -116,7 +116,6 @@ options KTRACE # system call tracing,
options DIAGNOSTIC # internal consistency checks
#options DEBUG
#options PMAP_DEBUG # Enable pmap_debug_level code
-#options VERBOSE_INIT_ARM # verbose bootstraping messages
options DDB # in-kernel debugger
options DDB_ONPANIC=1
options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
@@ -124,6 +123,10 @@ options DDB_HISTORY_SIZE=100 # Enable h
makeoptions DEBUG="-g" # compile full symbol table
makeoptions COPY_SYMTAB=1
+#options VERBOSE_INIT_ARM # verbose bootstraping messages
+#options EARLYCONS=beagle
+options CONSADDR=0x48020000, CONSPEED=115200
+
## USB Debugging options
options USB_DEBUG
options EHCI_DEBUG
@@ -198,7 +201,6 @@ gpio* at omapgpio?
# On-board 16550 UARTs
com0 at obio2 addr 0x48020000 intr 106 mult 4 # UART3 (console) 74+32
-options CONSADDR=0x48020000, CONSPEED=115200
# Operating System Timer
#omapmputmr0 at obio2 addr 0x48032000 intr 70 # GP Timer 2 L4PER
Index: src/sys/arch/evbarm/conf/PANDABOARD
diff -u src/sys/arch/evbarm/conf/PANDABOARD:1.28 src/sys/arch/evbarm/conf/PANDABOARD:1.29
--- src/sys/arch/evbarm/conf/PANDABOARD:1.28 Tue Oct 23 19:58:52 2018
+++ src/sys/arch/evbarm/conf/PANDABOARD Sat May 18 08:49:23 2019
@@ -1,5 +1,5 @@
#
-# $NetBSD: PANDABOARD,v 1.28 2018/10/23 19:58:52 jdolecek Exp $
+# $NetBSD: PANDABOARD,v 1.29 2019/05/18 08:49:23 skrll Exp $
#
# PANDABOARD -- TI OMAP 4430 Eval Board Kernel
#
@@ -114,7 +114,6 @@ options KTRACE # system call tracing,
options DIAGNOSTIC # internal consistency checks
#options DEBUG
#options PMAP_DEBUG # Enable pmap_debug_level code
-#options VERBOSE_INIT_ARM # verbose bootstraping messages
options DDB # in-kernel debugger
options DDB_ONPANIC=1
options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
@@ -122,6 +121,11 @@ options DDB_HISTORY_SIZE=100 # Enable h
makeoptions DEBUG="-g" # compile full symbol table
makeoptions COPY_SYMTAB=1
+#options VERBOSE_INIT_ARM # verbose bootstraping messages
+#options EARLYCONS=beagle
+#options CONSADDR=0x48020000, CONSPEED=38400
+options CONSADDR=0x48020000, CONSPEED=115200
+
## USB Debugging options
options USB_DEBUG
options EHCI_DEBUG
@@ -189,8 +193,6 @@ gpio* at omapgpio?
# On-board 16550 UARTs
com0 at obio2 addr 0x48020000 intr 106 mult 4 # UART3 (console)
-#options CONSADDR=0x48020000, CONSPEED=38400
-options CONSADDR=0x48020000, CONSPEED=115200
# Operating System Timer
#omapmputmr0 at obio2 addr 0x48032000 intr 70 # GP Timer 2 L4PER
Index: src/sys/arch/evbarm/conf/VTC100
diff -u src/sys/arch/evbarm/conf/VTC100:1.20 src/sys/arch/evbarm/conf/VTC100:1.21
--- src/sys/arch/evbarm/conf/VTC100:1.20 Tue Oct 23 19:58:52 2018
+++ src/sys/arch/evbarm/conf/VTC100 Sat May 18 08:49:23 2019
@@ -1,5 +1,5 @@
#
-# $NetBSD: VTC100,v 1.20 2018/10/23 19:58:52 jdolecek Exp $
+# $NetBSD: VTC100,v 1.21 2019/05/18 08:49:23 skrll Exp $
#
# VTC100 -- NEXCOM VTC100 Kernel
#
@@ -117,7 +117,6 @@ options KTRACE # system call tracing,
options DIAGNOSTIC # internal consistency checks
options DEBUG
#options PMAP_DEBUG # Enable pmap_debug_level code
-#options VERBOSE_INIT_ARM # verbose bootstraping messages
options DDB # in-kernel debugger
options DDB_ONPANIC=1
options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
@@ -125,6 +124,10 @@ options DDB_HISTORY_SIZE=100 # Enable h
makeoptions DEBUG="-g" # compile full symbol table
makeoptions COPY_SYMTAB=1
+#options VERBOSE_INIT_ARM # verbose bootstraping messages
+#options EARLYCONS=beagle
+options CONSADDR=0x48022000, CONSPEED=115200
+
## USB Debugging options
#options USB_DEBUG
#options MOTG_DEBUG
@@ -200,7 +203,7 @@ iic* at tiiic?
# On-board 16550 UARTs
com0 at obio1 addr 0x48022000 size 0x1000 intr 73 mult 4 # UART1
-options CONSADDR=0x48022000, CONSPEED=115200
+
# GPS
com1 at obio1 addr 0x481a6000 size 0x1000 intr 44 mult 4 # UART3
Index: src/sys/arch/evbarm/conf/mk.beagle
diff -u src/sys/arch/evbarm/conf/mk.beagle:1.11 src/sys/arch/evbarm/conf/mk.beagle:1.12
--- src/sys/arch/evbarm/conf/mk.beagle:1.11 Sat Mar 29 14:11:24 2014
+++ src/sys/arch/evbarm/conf/mk.beagle Sat May 18 08:49:23 2019
@@ -1,4 +1,4 @@
-# $NetBSD: mk.beagle,v 1.11 2014/03/29 14:11:24 matt Exp $
+# $NetBSD: mk.beagle,v 1.12 2019/05/18 08:49:23 skrll Exp $
.if ${KERNEL_BUILD:T:MPANDA*} != ""
CPPFLAGS+= -mcpu=cortex-a9
.elif ${KERNEL_BUILD:T:MOMAP5*} != ""
@@ -8,14 +8,12 @@ CPPFLAGS+= -mcpu=cortex-a8
.endif
CPPFLAGS+= -mfpu=neon
-SYSTEM_FIRST_OBJ= beagle_start.o
-SYSTEM_FIRST_SFILE= ${THISARM}/beagle/beagle_start.S
-
-GENASSYM_EXTRAS+= ${THISARM}/beagle/genassym.cf
+SYSTEM_FIRST_OBJ= armv6_start.o
+SYSTEM_FIRST_SFILE= ${ARM}/arm/armv6_start.S
_OSRELEASE!= ${HOST_SH} $S/conf/osrelease.sh
-MKUBOOTIMAGEARGS= -A arm -T kernel
+MKUBOOTIMAGEARGS= -A arm -T kernel -O linux
MKUBOOTIMAGEARGS+= -a $(LOADADDRESS) -e $(LOADADDRESS)
MKUBOOTIMAGEARGS+= -n "NetBSD/$(BOARDTYPE) ${_OSRELEASE}"
MKUBOOTIMAGEARGS_NONE= ${MKUBOOTIMAGEARGS} -C none
Index: src/sys/arch/evbarm/conf/mk.gumstix
diff -u src/sys/arch/evbarm/conf/mk.gumstix:1.6 src/sys/arch/evbarm/conf/mk.gumstix:1.7
--- src/sys/arch/evbarm/conf/mk.gumstix:1.6 Tue Oct 4 16:18:38 2016
+++ src/sys/arch/evbarm/conf/mk.gumstix Sat May 18 08:49:23 2019
@@ -1,22 +1,24 @@
-# $NetBSD: mk.gumstix,v 1.6 2016/10/04 16:18:38 kiyohara Exp $
+# $NetBSD: mk.gumstix,v 1.7 2019/05/18 08:49:23 skrll Exp $
+.if ${BOARDTYPE} == "gumstix"
SYSTEM_FIRST_OBJ= gumstix_start.o
SYSTEM_FIRST_SFILE= ${THISARM}/gumstix/gumstix_start.S
-_OSRELEASE!= ${HOST_SH} $S/conf/osrelease.sh
-
-.if ${BOARDTYPE} == "gumstix"
KERNEL_BASE_PHYS=0xa0200000
-.elif ${BOARDTYPE} == "overo"
-KERNEL_BASE_PHYS=$(LOADADDRESS)
-.elif ${BOARDTYPE} == "duovero"
-KERNEL_BASE_PHYS=$(LOADADDRESS)
-.elif ${BOARDTYPE} == "pepper"
+MKUBOOTEXTRAARGS=
+.else
+SYSTEM_FIRST_OBJ= armv6_start.o
+SYSTEM_FIRST_SFILE= ${ARM}/arm/armv6_start.S
+
KERNEL_BASE_PHYS=$(LOADADDRESS)
+MKUBOOTEXTRAARGS= -O linux
.endif
+
+_OSRELEASE!= ${HOST_SH} $S/conf/osrelease.sh
+
KERNEL_BASE_VIRT=$(LOADADDRESS)
-MKUBOOTIMAGEARGS= -A arm -T kernel
+MKUBOOTIMAGEARGS= -A arm -T kernel ${MKUBOOTEXTRAARGS}
MKUBOOTIMAGEARGS+= -a $(KERNEL_BASE_PHYS)
MKUBOOTIMAGEARGS+= -n "NetBSD/$(BOARDTYPE) ${_OSRELEASE}"
MKUBOOTIMAGEARGS_NONE= ${MKUBOOTIMAGEARGS} -C none
Index: src/sys/arch/evbarm/conf/mk.imx7
diff -u src/sys/arch/evbarm/conf/mk.imx7:1.1 src/sys/arch/evbarm/conf/mk.imx7:1.2
--- src/sys/arch/evbarm/conf/mk.imx7:1.1 Tue May 17 06:44:46 2016
+++ src/sys/arch/evbarm/conf/mk.imx7 Sat May 18 08:49:23 2019
@@ -1,16 +1,14 @@
-# $NetBSD: mk.imx7,v 1.1 2016/05/17 06:44:46 ryo Exp $
+# $NetBSD: mk.imx7,v 1.2 2019/05/18 08:49:23 skrll Exp $
-SYSTEM_FIRST_OBJ= imx7_start.o
-SYSTEM_FIRST_SFILE= ${THISARM}/imx7/imx7_start.S
-
-GENASSYM_EXTRAS+= ${THISARM}/imx7/genassym.cf
+SYSTEM_FIRST_OBJ= armv6_start.o
+SYSTEM_FIRST_SFILE= ${ARM}/arm/armv6_start.S
_OSRELEASE!= ${HOST_SH} $S/conf/osrelease.sh
KERNEL_BASE_PHYS?=$(LOADADDRESS)
KERNEL_BASE_VIRT?=$(LOADADDRESS)
-MKUBOOTIMAGEARGS= -A arm -T kernel
+MKUBOOTIMAGEARGS= -A arm -T kernel -O linux
MKUBOOTIMAGEARGS+= -a $(KERNEL_BASE_PHYS) -e $(KERNEL_BASE_PHYS)
MKUBOOTIMAGEARGS+= -n "NetBSD/$(BOARDTYPE) ${_OSRELEASE}"
MKUBOOTIMAGEARGS_NONE= ${MKUBOOTIMAGEARGS} -C none
Index: src/sys/arch/evbarm/conf/mk.kobo
diff -u src/sys/arch/evbarm/conf/mk.kobo:1.1 src/sys/arch/evbarm/conf/mk.kobo:1.2
--- src/sys/arch/evbarm/conf/mk.kobo:1.1 Fri Jul 25 11:22:50 2014
+++ src/sys/arch/evbarm/conf/mk.kobo Sat May 18 08:49:23 2019
@@ -1,11 +1,11 @@
-# $NetBSD: mk.kobo,v 1.1 2014/07/25 11:22:50 hkenken Exp $
+# $NetBSD: mk.kobo,v 1.2 2019/05/18 08:49:23 skrll Exp $
CPPFLAGS+= -mcpu=cortex-a8 -mfpu=neon
-SYSTEM_FIRST_OBJ= kobo_start.o
-SYSTEM_FIRST_SFILE= ${THISARM}/kobo/kobo_start.S
+SYSTEM_FIRST_OBJ= armv6_start.o
+SYSTEM_FIRST_SFILE= ${ARM}/arm/armv6_start.S
-MKUBOOTIMAGEARGS= -A arm -T kernel
+MKUBOOTIMAGEARGS= -A arm -T kernel -O linux
MKUBOOTIMAGEARGS+= -a $(LOADADDRESS) -e $(LOADADDRESS)
MKUBOOTIMAGEARGS+= -n "NetBSD/$(BOARDTYPE) ${_OSRELEASE}"
MKUBOOTIMAGEARGS_NONE= ${MKUBOOTIMAGEARGS} -C none
Index: src/sys/arch/evbarm/conf/mk.nitrogen6
diff -u src/sys/arch/evbarm/conf/mk.nitrogen6:1.3 src/sys/arch/evbarm/conf/mk.nitrogen6:1.4
--- src/sys/arch/evbarm/conf/mk.nitrogen6:1.3 Thu Oct 18 09:01:54 2018
+++ src/sys/arch/evbarm/conf/mk.nitrogen6 Sat May 18 08:49:23 2019
@@ -1,31 +1,25 @@
-# $NetBSD: mk.nitrogen6,v 1.3 2018/10/18 09:01:54 skrll Exp $
+# $NetBSD: mk.nitrogen6,v 1.4 2019/05/18 08:49:23 skrll Exp $
SYSTEM_FIRST_OBJ= armv6_start.o
SYSTEM_FIRST_SFILE= ${ARM}/arm/armv6_start.S
_OSRELEASE!= ${HOST_SH} $S/conf/osrelease.sh
-KERNEL_BASE_PHYS?=$(LOADADDRESS)
-KERNEL_BASE_VIRT?=$(LOADADDRESS)
+#KERNEL_BASE_PHYS?=$(LOADADDRESS)
+#KERNEL_BASE_VIRT?=$(LOADADDRESS)
-MKUBOOTIMAGEARGS= -A arm -T kernel -O linux
-MKUBOOTIMAGEARGS+= -a $(KERNEL_BASE_PHYS) -e $(KERNEL_BASE_PHYS)
+MKUBOOTIMAGEARGS= -A arm -T kernel_noload -O linux -C none
+MKUBOOTIMAGEARGS+= -e 0
MKUBOOTIMAGEARGS+= -n "NetBSD/$(BOARDTYPE) ${_OSRELEASE}"
-MKUBOOTIMAGEARGS_NONE= ${MKUBOOTIMAGEARGS} -C none
-MKUBOOTIMAGEARGS_GZ= ${MKUBOOTIMAGEARGS} -C gz
SYSTEM_LD_TAIL_EXTRA+=; \
echo ${OBJCOPY} -S -O binary $@ $@.bin; \
${OBJCOPY} -S -O binary $@ $@.bin; \
- echo ${TOOL_GZIP} -9c $@.bin > $@.bin.gz; \
- ${TOOL_GZIP} -9c $@.bin > $@.bin.gz; \
- echo ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_GZ} $@.bin.gz $@.gz.ub; \
- ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_GZ} $@.bin.gz $@.gz.ub; \
- echo ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_NONE} $@.bin $@.ub; \
- ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_NONE} $@.bin $@.ub; \
+ echo ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS} $@.bin $@.ub; \
+ ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS} $@.bin $@.ub; \
echo
EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.bin@}
EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.ub@}
EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.bin.gz@}
-EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.gz.ub@}
+
Index: src/sys/arch/evbarm/conf/std.bcm53xx
diff -u src/sys/arch/evbarm/conf/std.bcm53xx:1.19 src/sys/arch/evbarm/conf/std.bcm53xx:1.20
--- src/sys/arch/evbarm/conf/std.bcm53xx:1.19 Mon Jan 21 07:29:36 2019
+++ src/sys/arch/evbarm/conf/std.bcm53xx Sat May 18 08:49:23 2019
@@ -1,4 +1,4 @@
-# $NetBSD: std.bcm53xx,v 1.19 2019/01/21 07:29:36 skrll Exp $
+# $NetBSD: std.bcm53xx,v 1.20 2019/05/18 08:49:23 skrll Exp $
#
# standard NetBSD/evbarm for BCM5301X options
@@ -21,6 +21,7 @@ options _ARM32_NEED_BUS_DMA_BOUNCE
options __HAVE_CPU_COUNTER
options __HAVE_CPU_UAREA_ALLOC_IDLELWP
options __HAVE_FAST_SOFTINTS # should be in types.h
+options __HAVE_GENERIC_START
options __HAVE_MM_MD_CACHE_ALIASING
options __HAVE_MM_MD_DIRECT_MAPPED_PHYS
options __HAVE_PCI_CONF_HOOK
Index: src/sys/arch/evbarm/conf/std.gumstix
diff -u src/sys/arch/evbarm/conf/std.gumstix:1.10 src/sys/arch/evbarm/conf/std.gumstix:1.11
--- src/sys/arch/evbarm/conf/std.gumstix:1.10 Sun Oct 7 07:48:44 2018
+++ src/sys/arch/evbarm/conf/std.gumstix Sat May 18 08:49:23 2019
@@ -1,4 +1,4 @@
-# $NetBSD: std.gumstix,v 1.10 2018/10/07 07:48:44 skrll Exp $
+# $NetBSD: std.gumstix,v 1.11 2019/05/18 08:49:23 skrll Exp $
#
# standard NetBSD/evbarm for GUMSTIX options
@@ -7,13 +7,14 @@ include "arch/evbarm/conf/std.evbarm"
include "arch/evbarm/conf/files.gumstix"
+options ARM_INTR_IMPL="<arch/arm/xscale/pxa2x0_intr.h>"
+options EVBARM_BOARDTYPE=gumstix
options KERNEL_BASE_EXT=0xc0000000
-makeoptions LOADADDRESS="0xc0200000"
+options MD_CPU_HATCH=gumstix_cpu_hatch
+
makeoptions BOARDTYPE="gumstix"
-options EVBARM_BOARDTYPE=gumstix
makeoptions BOARDMKFRAG="${THISARM}/conf/mk.gumstix"
-
-options ARM_INTR_IMPL="<arch/arm/xscale/pxa2x0_intr.h>"
+makeoptions LOADADDRESS="0xc0200000"
# OS Timer
saost* at pxaip? addr 0x40a00000 size 0x20
Index: src/sys/arch/evbarm/conf/std.overo
diff -u src/sys/arch/evbarm/conf/std.overo:1.10 src/sys/arch/evbarm/conf/std.overo:1.11
--- src/sys/arch/evbarm/conf/std.overo:1.10 Mon Oct 15 16:54:54 2018
+++ src/sys/arch/evbarm/conf/std.overo Sat May 18 08:49:23 2019
@@ -1,4 +1,4 @@
-# $NetBSD: std.overo,v 1.10 2018/10/15 16:54:54 skrll Exp $
+# $NetBSD: std.overo,v 1.11 2019/05/18 08:49:23 skrll Exp $
#
# standard NetBSD/evbarm for OVERO options
@@ -7,12 +7,13 @@ include "arch/evbarm/conf/std.evbarm"
include "arch/evbarm/conf/files.overo"
+options ARM_GENERIC_TODR
+options ARM_INTR_IMPL="<arch/arm/omap/omap2_intr.h>"
options CORTEX_PMC
-options __HAVE_FAST_SOFTINTS # should be in types.h
+options MD_CPU_HATCH=gumstix_cpu_hatch
options TPIDRPRW_IS_CURCPU
+options __HAVE_FAST_SOFTINTS # should be in types.h
+options __HAVE_GENERIC_START
makeoptions LOADADDRESS="0x80200000"
makeoptions BOARDMKFRAG="${THISARM}/conf/mk.gumstix"
-
-options ARM_INTR_IMPL="<arch/arm/omap/omap2_intr.h>"
-options ARM_GENERIC_TODR
Index: src/sys/arch/evbarm/conf/std.imx7
diff -u src/sys/arch/evbarm/conf/std.imx7:1.4 src/sys/arch/evbarm/conf/std.imx7:1.5
--- src/sys/arch/evbarm/conf/std.imx7:1.4 Mon Oct 15 16:54:54 2018
+++ src/sys/arch/evbarm/conf/std.imx7 Sat May 18 08:49:23 2019
@@ -1,4 +1,4 @@
-# $NetBSD: std.imx7,v 1.4 2018/10/15 16:54:54 skrll Exp $
+# $NetBSD: std.imx7,v 1.5 2019/05/18 08:49:23 skrll Exp $
#
# standard NetBSD/evbarm options for i.MX7 board
@@ -8,27 +8,25 @@ include "arch/evbarm/conf/std.evbarm"
# Pull in imx7 config definitions.
include "arch/evbarm/conf/files.imx7"
-options IMX7BOARD
-
+options ARM_GENERIC_TODR
options ARM_HAS_VBAR
+options ARM_INTR_IMPL="<arch/arm/imx/imx7_intr.h>"
+options CORTEX_PMC
+options CORTEX_PMC_CCNT_HZ=792000000
+options FPU_VFP
+options IMX7BOARD
+options MD_CPU_HATCH=imx7_cpu_hatch
+options TPIDRPRW_IS_CURCPU
options __HAVE_CPU_COUNTER
options __HAVE_FAST_SOFTINTS # should be in types.h
options __HAVE_CPU_UAREA_ALLOC_IDLELWP
+options __HAVE_GENERIC_START
options __HAVE_MM_MD_DIRECT_MAPPED_PHYS
-options TPIDRPRW_IS_CURCPU
makeoptions CPUFLAGS="-mcpu=cortex-a7 -mfpu=neon"
-# To support easy transit to ../arch/arm/arm32
-options FPU_VFP
-options CORTEX_PMC
-options CORTEX_PMC_CCNT_HZ=792000000
-
-makeoptions KERNEL_BASE_PHYS="0x82000000"
-makeoptions KERNEL_BASE_VIRT="0x82000000"
-
makeoptions BOARDMKFRAG="${THISARM}/conf/mk.imx7"
makeoptions CPPFLAGS+="-I$S/../../../include"
+makeoptions KERNEL_BASE_PHYS="0x82000000"
+makeoptions KERNEL_BASE_VIRT="0x82000000"
-options ARM_INTR_IMPL="<arch/arm/imx/imx7_intr.h>"
-options ARM_GENERIC_TODR
Index: src/sys/arch/evbarm/conf/std.kobo
diff -u src/sys/arch/evbarm/conf/std.kobo:1.4 src/sys/arch/evbarm/conf/std.kobo:1.5
--- src/sys/arch/evbarm/conf/std.kobo:1.4 Mon Oct 15 16:54:54 2018
+++ src/sys/arch/evbarm/conf/std.kobo Sat May 18 08:49:23 2019
@@ -1,4 +1,4 @@
-# $NetBSD: std.kobo,v 1.4 2018/10/15 16:54:54 skrll Exp $
+# $NetBSD: std.kobo,v 1.5 2019/05/18 08:49:23 skrll Exp $
#
# standard NetBSD/evbarm options for Kobo
@@ -8,22 +8,22 @@ include "arch/evbarm/conf/std.evbarm"
# Pull in i.mx51 config definitions.
include "arch/evbarm/conf/files.kobo"
-options MODULAR
-options MODULAR_DEFAULT_AUTOLOAD
-options __HAVE_FAST_SOFTINTS # should be in types.h
-options __HAVE_CPU_COUNTER
-options __HAVE_MM_MD_DIRECT_MAPPED_PHYS
-options __HAVE_CPU_UAREA_ALLOC_IDLELWP
+options ARM_GENERIC_TODR
options ARM_HAS_VBAR
-options TPIDRPRW_IS_CURCPU
+options ARM_INTR_IMPL="<arch/arm/imx/imx51_intr.h>"
options CORTEX_PMC
options CORTEX_PMC_CCNT_HZ=800000000
options EVBARM_BOARDTYPE="kobo"
options FPU_VFP
+options MODULAR
+options MODULAR_DEFAULT_AUTOLOAD
+options TPIDRPRW_IS_CURCPU
+options __HAVE_CPU_COUNTER
+options __HAVE_CPU_UAREA_ALLOC_IDLELWP
+options __HAVE_FAST_SOFTINTS # should be in types.h
+options __HAVE_GENERIC_START
+options __HAVE_MM_MD_DIRECT_MAPPED_PHYS
makeoptions LOADADDRESS_VIRT="0x80100000"
makeoptions LOADADDRESS="0x70100000"
makeoptions BOARDMKFRAG="${THISARM}/conf/mk.kobo"
-
-options ARM_INTR_IMPL="<arch/arm/imx/imx51_intr.h>"
-options ARM_GENERIC_TODR
Index: src/sys/arch/evbarm/conf/std.nitrogen6
diff -u src/sys/arch/evbarm/conf/std.nitrogen6:1.9 src/sys/arch/evbarm/conf/std.nitrogen6:1.10
--- src/sys/arch/evbarm/conf/std.nitrogen6:1.9 Thu Oct 18 09:01:54 2018
+++ src/sys/arch/evbarm/conf/std.nitrogen6 Sat May 18 08:49:23 2019
@@ -1,4 +1,4 @@
-# $NetBSD: std.nitrogen6,v 1.9 2018/10/18 09:01:54 skrll Exp $
+# $NetBSD: std.nitrogen6,v 1.10 2019/05/18 08:49:23 skrll Exp $
#
# standard NetBSD/evbarm options for Nitrogen6X
@@ -27,5 +27,8 @@ options __HAVE_GENERIC_START
makeoptions BOARDMKFRAG="${THISARM}/conf/mk.nitrogen6"
makeoptions CPPFLAGS+="-I$S/../../../include"
makeoptions CPUFLAGS="-mcpu=cortex-a9"
-makeoptions KERNEL_BASE_PHYS="0x18000000"
-makeoptions KERNEL_BASE_VIRT="0x80000000"
+
+# The physical address is chosen by u-boot and determined by armv6_start.S.
+# The 64 byte offset is due to u-boot header.
+makeoptions KERNEL_BASE_PHYS="0x00000040"
+makeoptions KERNEL_BASE_VIRT="0x80000040"
Index: src/sys/arch/evbarm/gumstix/gumstix_machdep.c
diff -u src/sys/arch/evbarm/gumstix/gumstix_machdep.c:1.61 src/sys/arch/evbarm/gumstix/gumstix_machdep.c:1.62
--- src/sys/arch/evbarm/gumstix/gumstix_machdep.c:1.61 Fri Sep 21 12:04:08 2018
+++ src/sys/arch/evbarm/gumstix/gumstix_machdep.c Sat May 18 08:49:24 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gumstix_machdep.c,v 1.61 2018/09/21 12:04:08 skrll Exp $ */
+/* $NetBSD: gumstix_machdep.c,v 1.62 2019/05/18 08:49:24 skrll Exp $ */
/*
* Copyright (C) 2005, 2006, 2007 WIDE Project and SOUM Corporation.
* All rights reserved.
@@ -179,10 +179,7 @@
#include <arm/locore.h>
#include <arm/arm32/machdep.h>
-#if NARML2CC > 0
-#include <arm/cortex/pl310_var.h>
-#endif
-#include <arm/cortex/scu_reg.h>
+
#include <arm/omap/omap2_obiovar.h>
#include <arm/omap/am335x_prcm.h>
#include <arm/omap/omap2_gpio.h>
@@ -195,18 +192,37 @@
#include <arm/omap/omap_var.h>
#include <arm/omap/omap_com.h>
#include <arm/omap/tifbvar.h>
+
#include <arm/xscale/pxa2x0reg.h>
#include <arm/xscale/pxa2x0var.h>
#include <arm/xscale/pxa2x0_gpio.h>
#include <evbarm/gumstix/gumstixreg.h>
#include <evbarm/gumstix/gumstixvar.h>
+#if defined(CPU_CORTEXA9)
+#include <arm/cortex/pl310_var.h>
+#include <arm/cortex/pl310_reg.h>
+#include <arm/cortex/scu_reg.h>
+
+#include <arm/cortex/a9tmr_var.h>
+#endif
+
+#if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15)
+#include <arm/cortex/gtmr_var.h>
+#endif
+
#include <dev/cons.h>
#ifdef KGDB
#include <sys/kgdb.h>
#endif
+#ifdef VERBOSE_INIT_ARM
+#define VPRINTF(...) printf(__VA_ARGS__)
+#else
+#define VPRINTF(...) __nothing
+#endif
+
/*
* The range 0xc1000000 - 0xfd000000 is available for kernel VM space
* Core-logic registers and I/O mappings occupy
@@ -391,6 +407,13 @@ static const struct pmap_devmap gumstix_
VM_PROT_READ | VM_PROT_WRITE,
PTE_NOCACHE
},
+ {
+ OVERO_SRDC_VBASE,
+ _A(OMAP3530_SDRC_BASE),
+ _S(OMAP3530_SDRC_SIZE),
+ VM_PROT_READ | VM_PROT_WRITE,
+ PTE_NOCACHE
+ },
#elif defined(DUOVERO)
{
DUOVERO_L4_CM_VBASE,
@@ -420,6 +443,13 @@ static const struct pmap_devmap gumstix_
VM_PROT_READ | VM_PROT_WRITE,
PTE_NOCACHE
},
+ {
+ DUOVERO_DMM_VBASE,
+ _A(OMAP4430_DMM_BASE),
+ _S(OMAP4430_DMM_SIZE),
+ VM_PROT_READ | VM_PROT_WRITE,
+ PTE_NOCACHE
+ },
#elif defined(PEPPER)
{
/* CM, Control Module, GPIO0, Console */
@@ -444,6 +474,95 @@ static const struct pmap_devmap gumstix_
#undef _A
#undef _S
+#ifdef MULTIPROCESSOR
+void gumstix_cpu_hatch(struct cpu_info *);
+
+void
+gumstix_cpu_hatch(struct cpu_info *ci)
+{
+#if defined(CPU_CORTEXA9)
+ a9tmr_init_cpu_clock(ci);
+#elif defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15)
+ gtmr_init_cpu_clock(ci);
+#endif
+}
+#endif
+
+
+static void
+gumstix_mpstart(void)
+{
+#if defined(MULTIPROCESSOR)
+ const bus_space_tag_t iot = &omap_bs_tag;
+ int error;
+
+#if defined(CPU_CORTEXA9)
+ bus_space_handle_t scu_ioh;
+ error = bus_space_map(iot, OMAP4_SCU_BASE, OMAP4_SCU_SIZE, 0, &scu_ioh);
+ if (error)
+ panic("Could't map OMAP4_SCU_BASE");
+
+ /*
+ * Invalidate all SCU cache tags. That is, for all cores (0-3)
+ */
+ bus_space_write_4(iot, scu_ioh, SCU_INV_ALL_REG, 0xffff);
+
+ uint32_t diagctl = bus_space_read_4(iot, scu_ioh, SCU_DIAG_CONTROL);
+ diagctl |= SCU_DIAG_DISABLE_MIGBIT;
+ bus_space_write_4(iot, scu_ioh, SCU_DIAG_CONTROL, diagctl);
+
+ uint32_t scu_ctl = bus_space_read_4(iot, scu_ioh, SCU_CTL);
+ scu_ctl |= SCU_CTL_SCU_ENA;
+ bus_space_write_4(iot, scu_ioh, SCU_CTL, scu_ctl);
+
+ armv7_dcache_wbinv_all();
+#endif
+ bus_space_handle_t wugen_ioh;
+ error = bus_space_map(iot, OMAP4_WUGEN_BASE, OMAP4_WUGEN_SIZE, 0,
+ &wugen_ioh);
+ if (error)
+ panic("Couldn't map OMAP4_WUGEN_BASE");
+ const paddr_t mpstart = KERN_VTOPHYS((vaddr_t)cpu_mpstart);
+
+ bus_space_write_4(iot, wugen_ioh, OMAP4_AUX_CORE_BOOT1, mpstart);
+
+ for (size_t i = 1; i < arm_cpu_max; i++) {
+ uint32_t boot = bus_space_read_4(iot, wugen_ioh, OMAP4_AUX_CORE_BOOT0);
+ boot |= __SHIFTIN(0xf, i * 4);
+ bus_space_write_4(iot, wugen_ioh, OMAP4_AUX_CORE_BOOT0, boot);
+ }
+
+ arm_dsb();
+ __asm __volatile("sev" ::: "memory");
+
+ for (int loop = 0; loop < 16; loop++) {
+ VPRINTF("%u hatched %#x\n", loop, arm_cpu_hatched);
+ if (arm_cpu_hatched == __BITS(arm_cpu_max - 1, 1))
+ break;
+ int timo = 1500000;
+ while (arm_cpu_hatched != __BITS(arm_cpu_max - 1, 1))
+ if (--timo == 0)
+ break;
+ }
+ for (size_t i = 1; i < arm_cpu_max; i++) {
+ if ((arm_cpu_hatched & __BIT(i)) == 0) {
+ printf("%s: warning: cpu%zu failed to hatch\n",
+ __func__, i);
+ }
+ }
+
+ VPRINTF(" (%u cpu%s, hatched %#x)",
+ arm_cpu_max, arm_cpu_max ? "s" : "",
+ arm_cpu_hatched);
+#endif
+}
+
+#if defined(CPU_CORTEX)
+/* filled in before cleaning bss. keep in .data */
+u_int uboot_args[4] __attribute__((__section__(".data")));
+#else
+extern uint32_t *uboot_args;
+#endif
/*
* u_int initarm(...)
@@ -462,10 +581,15 @@ u_int
initarm(void *arg)
{
extern char KERNEL_BASE_phys[];
- extern uint32_t *u_boot_args[];
- extern uint32_t ram_size;
+ uint32_t ram_size = 0x400000;
enum { r0 = 0, r1 = 1, r2 = 2, r3 = 3 }; /* args from u-boot */
+#if defined(OVERO) || defined(DUOVERO) /* || defined(PEPPER) */
+ const bus_space_tag_t iot = &omap_bs_tag;
+#endif
+
+#if defined(CPU_XSCALE)
+
/*
* We mapped PA == VA in gumstix_start.S.
* Also mapped SDRAM to KERNEL_BASE first 64Mbyte only with cachable.
@@ -477,21 +601,7 @@ initarm(void *arg)
* 0x40000000 - 0x480fffff Processor Registers
* 0xa0000000 - 0xa3ffffff SDRAM Bank 0 (64MB or 128MB)
* 0xc0000000 - 0xc3ffffff KERNEL_BASE
- *
- * Overo:
- * Physical Address Range Description
- * ----------------------- ----------------------------------
- * 0x80000000 - 0x9fffffff SDRAM Bank 0
- * 0x80000000 - 0x83ffffff KERNEL_BASE
- *
- * DuoVero, Pepper:
- * Physical Address Range Description
- * ----------------------- ----------------------------------
- * 0x80000000 - 0xbfffffff SDRAM Bank 0
- * 0x80000000 - 0x83ffffff KERNEL_BASE
*/
-
-#if defined(CPU_XSCALE)
extern vaddr_t xscale_cache_clean_addr;
xscale_cache_clean_addr = 0xff000000U;
@@ -524,6 +634,62 @@ initarm(void *arg)
pxa2x0_clkman_bootstrap(GUMSTIX_CLKMAN_VBASE);
#endif
+
+#if defined(OVERO)
+
+#define OMAP3530_SRDC_MCFG_p(p) (0x80 + ((p) * 0x30))
+#define OMAP3530_SRDC_MCFG_RAMSIZE __BITS(17,8)
+
+ bus_space_handle_t sdrcioh;
+ if (bus_space_map(iot, OMAP3530_SDRC_BASE, OMAP3530_SDRC_SIZE,
+ 0, &sdrcioh) != 0)
+ panic("OMAP_SDRC_BASE map failed\n");
+
+ ram_size = 0;
+ for (u_int p = 0; p < 2; p++) {
+ uint32_t mcfg = bus_space_read_4(iot, sdrcioh,
+ OMAP3530_SRDC_MCFG_p(p));
+ ram_size += __SHIFTOUT(mcfg, OMAP3530_SRDC_MCFG_RAMSIZE) *
+ (2 * 1024 * 1024);
+ }
+
+#elif defined(DUOVERO)
+
+#define OMAP4_DMM_LISA_MAP_i(i) (0x40 + ((i) * 0x4))
+#define OMAP4_DMM_LISA_SYS_ADDR __BITS(31,24)
+#define OMAP4_DMM_LISA_SYS_SIZE __BITS(22,20)
+#define OMAP4_DMM_LISA_SDRC_ADDRSPC __BITS(17,16)
+
+ bus_space_handle_t dmmioh;
+ if (bus_space_map(iot, OMAP4430_DMM_BASE, OMAP4430_DMM_SIZE, 0,
+ &dmmioh) != 0)
+ panic("OMAP4_DMM_BASE map failed\n");
+
+ ram_size = 0;
+ for (u_int i = 0; i < 4; i++) {
+ const uint32_t lisa = bus_space_read_4(iot, dmmioh,
+ OMAP4_DMM_LISA_MAP_i(i));
+
+ const uint32_t sys_addr =
+ __SHIFTOUT(lisa, OMAP4_DMM_LISA_SYS_ADDR);
+ /* skip non-physical */
+ if ((sys_addr & 0x80) != 0)
+ continue;
+
+ const uint32_t sdrc_addrspc =
+ __SHIFTOUT(lisa, OMAP4_DMM_LISA_SDRC_ADDRSPC);
+ /* Skip reserced areas */
+ if (sdrc_addrspc == 2)
+ continue;
+
+ const uint32_t sys_size =
+ __SHIFTOUT(lisa, OMAP4_DMM_LISA_SYS_SIZE);
+ ram_size += (16 * 1024 * 1024) << sys_size;
+ }
+
+
+#endif
+
cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
/* configure MUX, GPIO and CLK. */
@@ -545,17 +711,16 @@ initarm(void *arg)
#elif defined(OVERO) || defined(DUOVERO) || defined(PEPPER)
#define SDRAM_START 0x80000000UL
#endif
- if ((uint32_t)u_boot_args[r0] < SDRAM_START ||
- (uint32_t)u_boot_args[r0] >= SDRAM_START + ram_size)
+ if (uboot_args[r0] < SDRAM_START ||
+ uboot_args[r0] >= SDRAM_START + ram_size)
/* Maybe r0 is 'argc'. We are booted by command 'go'. */
- process_kernel_args((int)u_boot_args[r0],
- (char **)u_boot_args[r1]);
+ process_kernel_args(uboot_args[r0], (char **)uboot_args[r1]);
else
/*
* Maybe r3 is 'boot args string' of 'bootm'. This string is
* linely.
*/
- process_kernel_args_liner((char *)u_boot_args[r3]);
+ process_kernel_args_liner((char *)uboot_args[r3]);
#ifdef GUMSTIX_NETBSD_ARGS_CONSOLE
consinit();
#endif
@@ -570,12 +735,9 @@ initarm(void *arg)
read_system_serial();
#endif
-#ifdef VERBOSE_INIT_ARM
- printf("initarm: Configuring system ...\n");
-#endif
+ VPRINTF("initarm: Configuring system ...\n");
#if defined(OMAP_4430)
- const bus_space_tag_t iot = &omap_bs_tag;
bus_space_handle_t ioh;
#if NARML2CC > 0
@@ -616,7 +778,14 @@ initarm(void *arg)
evbarm_device_register = gumstix_device_register;
- return initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0);
+ u_int sp = initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0);
+
+ /*
+ * initarm_common flushes cache if required before AP start
+ */
+ gumstix_mpstart();
+
+ return sp;
}
#if defined(GUMSTIX)
Index: src/sys/arch/evbarm/gumstix/gumstix_start.S
diff -u src/sys/arch/evbarm/gumstix/gumstix_start.S:1.15 src/sys/arch/evbarm/gumstix/gumstix_start.S:1.16
--- src/sys/arch/evbarm/gumstix/gumstix_start.S:1.15 Mon Jan 2 21:46:59 2017
+++ src/sys/arch/evbarm/gumstix/gumstix_start.S Sat May 18 08:49:24 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gumstix_start.S,v 1.15 2017/01/02 21:46:59 skrll Exp $ */
+/* $NetBSD: gumstix_start.S,v 1.16 2019/05/18 08:49:24 skrll Exp $ */
/*
* Copyright (C) 2005, 2006 WIDE Project and SOUM Corporation.
* All rights reserved.
@@ -67,11 +67,8 @@
#include <arm/armreg.h>
#include "assym.h"
-#if defined(OVERO) || defined(DUOVERO) || defined(PEPPER)
-#include <arm/omap/omap2_obioreg.h>
-#endif
-RCSID("$NetBSD: gumstix_start.S,v 1.15 2017/01/02 21:46:59 skrll Exp $")
+RCSID("$NetBSD: gumstix_start.S,v 1.16 2019/05/18 08:49:24 skrll Exp $")
/*
* CPWAIT -- Canonical method to wait for CP15 update.
@@ -111,12 +108,11 @@ _C_LABEL(gumstix_start):
/*
* Kernel is loaded in SDRAM (0xa0200000..), and is expected to run
- * in VA 0xc0200000.. (GUMSTIX)
- * VA == PA if OVERO.
+ * in VA 0xc0200000..
*/
/* save u-boot's args */
- adr ip, u_boot_args
+ adr ip, uboot_args
nop
nop
nop
@@ -127,15 +123,12 @@ _C_LABEL(gumstix_start):
/* Calculate RAM size, like vendor's u-boot. */
adr ip, ram_size
-#if defined(GUMSTIX) || defined(PEPPER)
ldr r0, [ip]
-#if defined(GUMSTIX)
mrc p15, 0, r1, c0, c0, 0
and r1, r1, #CPU_ID_XSCALE_COREGEN_MASK
cmp r1, #0x4000
bne 3f /* goto 3f, if basix or connex */
-#endif
0:
/* check memory size, if verdex or verdex-pro */
add r3, ip, r0
@@ -155,39 +148,6 @@ _C_LABEL(gumstix_start):
str r0, [r3] /* restore */
b 1b
3:
-#elif defined(OVERO)
- mov r1, #0x7f000000 /* mask */
- orr r1, r1, #0x00e00000 /* mask */
- mov r3, #0x6d000000 /* OMAP34xx SDRC */
- add r3, r3, #0x0080 /* CS0 MCFG */
- ldr r2, [r3]
- and r0, r1, r2, lsl #13
- add r3, r3, #0x0030 /* CS1 MCFG */
- ldr r2, [r3]
- and r2, r1, r2, lsl #13
- add r0, r0, r2
-#elif defined(DUOVERO)
- mov r0, #0
- mov r3, #0x4e000000 /* OMAP44xx DMM */
- add r3, r3, #0x0050
-0:
- ldr r2, [r3, #-4]! /* DMM_LISA_MAP_[3210] */
- and r1, r2, #0xff000000 /* get SYS_ADDR */
- tst r1, #0x80000000 /* is physical mem? */
- beq 1f
- and r1, r2, #0x00030000 /* get SDRC_ADDRSPC */
- cmp r1, #0x00020000 /* is Reserved? */
- beq 1f
-
- lsr r2, r2, #20
- and r1, r2, #0x7 /* get SYS_SIZE */
- mov r2, #0x01000000
- mov r2, r2, lsl r1
- add r0, r0, r2
-1:
- tst r3, #0x0000000f
- bne 0b
-#endif
str r0, [ip]
/* Build page table from scratch */
@@ -207,26 +167,9 @@ _C_LABEL(gumstix_start):
cmp r1, #0
bne 4b
-#if defined(CPU_CORTEX)
- mrc p15, 0, r1, c0, c0, 5 /* Read MPIDR */
- cmp r1, #0 /* Check MPIDR_MP (bit 31) */
- orrlt r1, r0, #TTBR_MPATTR
- orrge r1, r0, #TTBR_UPATTR
-#else
mov r1, r0
-#endif
mcr p15, 0, r1, c2, c0, 0 /* Set TTB */
mcr p15, 0, r1, c8, c7, 0 /* Flush TLB */
-#if defined(CPU_CORTEX)
- mcr p15, 0, r1, c2, c0, 1 /* Set TTB1 */
- mov r1, #TTBCR_S_N_1
- mcr p15, 0, r1, c2, c0, 2 /* Set TTBCR */
- mov r1, #0
- mcr p15, 0, r1, c8, c7, 0 /* Flush TLB */
-
- mov r1, #0
- mcr p15, 0, r1, c13, c0, 1 /* Write KERNEL_PID(#0) to CONTEXTIDR */
-#endif
/*
* Set the Domain Access register. Very important!
@@ -241,17 +184,6 @@ _C_LABEL(gumstix_start):
#if defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270)
orr r1, r1, #CPU_CONTROL_SYST_ENABLE
#endif
-#if defined(CPU_CORTEX)
-#if defined(CPU_CORTEXA8)
- /* Disable L2 cache beforehand. */
- mrc p15, 0, r2, c1, c0, 1
- bic r2, r2, #0x2 /* clear L2EN */
- mcr p15, 0, r2, c1, c0, 1
-#endif
-
- orr r1, r1, #(CPU_CONTROL_AFLT_ENABLE | CPU_CONTROL_DC_ENABLE)
- orr r1, r1, #(CPU_CONTROL_BPRD_ENABLE | CPU_CONTROL_IC_ENABLE)
-#endif
orr r1, r1, #CPU_CONTROL_MMU_ENABLE
mcr p15, 0, r1, c1, c0, 0
/*
@@ -259,9 +191,6 @@ _C_LABEL(gumstix_start):
*/
CPWAIT(r3)
-#if defined(MULTIPROCESSOR)
- bl omap_a9_mpinit /* omap_a9_mpinit(r0) */
-#endif
/* Jump to kernel code in TRUE VA */
ldr r0, Lstart
@@ -271,8 +200,8 @@ Lstart:
.word start
- .globl _C_LABEL(u_boot_args)
-u_boot_args:
+ .globl _C_LABEL(uboot_args)
+uboot_args:
.space 16 /* r0, r1, r2, r3 */
.globl _C_LABEL(ram_size)
@@ -281,11 +210,7 @@ ram_size:
#ifndef STARTUP_PAGETABLE_ADDR
-#if defined(GUMSTIX)
#define STARTUP_PAGETABLE_ADDR 0xa0000000 /* aligned 16kByte */
-#elif defined(OVERO) || defined(DUOVERO) || defined(PEPPER)
-#define STARTUP_PAGETABLE_ADDR 0x80000000 /* aligned 16kByte */
-#endif
#endif
Lstartup_pagetable:
.word STARTUP_PAGETABLE_ADDR
@@ -297,7 +222,6 @@ Lstartup_pagetable:
.word (pa) | (attr) ;
mmu_init_table:
-#if defined(GUMSTIX)
/* fill all table VA==PA */
MMU_INIT(0x00000000, 0x00000000,
@@ -313,101 +237,8 @@ mmu_init_table:
MMU_INIT(0xc0000000, SDRAM_START,
64, L1_S_PROTO | L1_S_C | L1_S_AP_KRW)
-#elif defined(OVERO) || defined(DUOVERO) || defined(PEPPER)
-
- /* fill all table VA==PA */
- MMU_INIT(0x00000000, 0x00000000,
- 1 << (32 - L1_S_SHIFT), L1_S_PROTO | L1_S_APv7_KRW | L1_S_V6_XN)
-
-#define SDRAM_START 0x80000000
-
- /* Map VA to PA, write-back cacheable (first 64M only) */
- MMU_INIT(KERNEL_BASE & 0xffffffff, SDRAM_START,
- 64,
-#if defined(MULTIPROCESSOR)
- L1_S_PROTO | L1_S_V6_S | L1_S_B | L1_S_C | L1_S_APv7_KRW
-#else
- L1_S_PROTO | L1_S_B | L1_S_C | L1_S_APv7_KRW
-#endif
- )
-
-#endif
MMU_INIT(0, 0, 0, 0) /* end of table */
#undef MMU_INIT
-#if defined(MULTIPROCESSOR)
-#define XPUTC(n)
-
-#define MD_CPU_HATCH _C_LABEL(a9tmr_init_cpu_clock)
-
-#include <arm/cortex/pl310_reg.h>
-#include <arm/cortex/a9_mpsubr.S>
-
-omap_a9_mpinit:
- mrc p15, 0, r1, c0, c0, 5 /* Read MPIDR */
- and r1, r1, #(MPIDR_MP | MPIDR_U)
- cmp r1, #MPIDR_MP
- bxne lr /* not MP */
-
- /* Invalidate CPU0 ways */
- mrc p15, 4, r3, c15, c0, 0;
- mov r1, #0xf;
- str r1, [r3, #SCU_INV_ALL_REG]
- dsb
- isb
-
- ldr r1, [r3, #SCU_CTL]
- orr r1, r1, #SCU_CTL_SCU_ENA
- str r1, [r3, #SCU_CTL]
- dsb
- isb
-
- movw r1, #:lower16:cortex_mmuinfo
- movt r1, #:upper16:cortex_mmuinfo
- str r0, [r1]
- /* Make sure the info makes into memory */
- mcr p15, 0, r1, c7, c10, 1 /* writeback the L1 cache line */
- dsb
- add r3, r3, #0x2000 /* PL310 L2 Cache controller */
- str r1, [r3, #L2C_CLEAN_PA] /* L2 cache also writeback */
- mov r0, #0
- str r0, [r3, #L2C_CACHE_SYNC]
-0:
- ldr r0, [r3, #L2C_CACHE_SYNC]
- tst r0, #0x1
- bne 0b
-
- movw r3, #:lower16:OMAP4_WUGEN_BASE
- movt r3, #:upper16:OMAP4_WUGEN_BASE
-
- /* First we setup the address for the secondaries to jump to. */
- adr r0, cortex_mpstart
- str r0, [r3, #OMAP4_AUX_CORE_BOOT1]
- dsb
-
- /* tell the secondary boot rom(s) to exit their loop */
- ldr r1, [r3, #OMAP4_AUX_CORE_BOOT0]
- orr r1, r1, #0xf0 /* add mask for cpu #1 */
- str r1, [r3, #OMAP4_AUX_CORE_BOOT0]
- dsb
-
- /* Now we kick it and return. */
- sev
- movw r3, #:lower16:arm_cpu_hatched
- movt r3, #:upper16:arm_cpu_hatched
-
- /* Let's wait for the secondary to hatch. */
- mov r1, #0x1000000
-1: dmb
- ldr r0, [r3]
- cmp r0, #0
- bxne lr
- subs r1, r1, #1
- bne 1b
-
- bx lr
-
-END(omap_a9_mpinit)
-#endif /* MULTIPROCESSOR */
Index: src/sys/arch/evbarm/gumstix/gumstixreg.h
diff -u src/sys/arch/evbarm/gumstix/gumstixreg.h:1.9 src/sys/arch/evbarm/gumstix/gumstixreg.h:1.10
--- src/sys/arch/evbarm/gumstix/gumstixreg.h:1.9 Sat Oct 15 16:30:46 2016
+++ src/sys/arch/evbarm/gumstix/gumstixreg.h Sat May 18 08:49:24 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: gumstixreg.h,v 1.9 2016/10/15 16:30:46 kiyohara Exp $ */
+/* $NetBSD: gumstixreg.h,v 1.10 2019/05/18 08:49:24 skrll Exp $ */
/*
* Copyright (C) 2005, 2006 WIDE Project and SOUM Corporation.
* All rights reserved.
@@ -51,11 +51,13 @@
#define OVERO_L4_PERIPHERAL_VBASE 0xc0100000
#define OVERO_L4_WAKEUP_VBASE 0xc0200000
#define OVERO_GPMC_VBASE 0xc0300000
+#define OVERO_SRDC_VBASE 0xc0400000
#define DUOVERO_L4_CM_VBASE 0xc0000000
#define DUOVERO_L4_PERIPHERAL_VBASE 0xc0100000
#define DUOVERO_L4_WAKEUP_VBASE 0xc0400000
#define DUOVERO_GPMC_VBASE 0xc0500000
+#define DUOVERO_DMM_VBASE 0xc1000000
#define PEPPER_PRCM_VBASE 0xc0000000
#define PEPPER_L4_PERIPHERAL_VBASE 0xc0100000
Index: src/sys/arch/evbarm/imx7/imx7_machdep.c
diff -u src/sys/arch/evbarm/imx7/imx7_machdep.c:1.9 src/sys/arch/evbarm/imx7/imx7_machdep.c:1.10
--- src/sys/arch/evbarm/imx7/imx7_machdep.c:1.9 Fri Sep 21 12:04:08 2018
+++ src/sys/arch/evbarm/imx7/imx7_machdep.c Sat May 18 08:49:24 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: imx7_machdep.c,v 1.9 2018/09/21 12:04:08 skrll Exp $ */
+/* $NetBSD: imx7_machdep.c,v 1.10 2019/05/18 08:49:24 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx7_machdep.c,v 1.9 2018/09/21 12:04:08 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx7_machdep.c,v 1.10 2019/05/18 08:49:24 skrll Exp $");
#include "opt_evbarm_boardtype.h"
#include "opt_arm_debug.h"
@@ -62,10 +62,18 @@ __KERNEL_RCSID(0, "$NetBSD: imx7_machdep
#include <machine/bootconfig.h>
#include <arm/imx/imx7var.h>
+#include <arm/imx/imx7_srcreg.h>
#include <arm/imx/imxuartvar.h>
+#include <arm/imx/imxuartreg.h>
#include <evbarm/imx7/platform.h>
+#ifdef VERBOSE_INIT_ARM
+#define VPRINTF(...) printf(__VA_ARGS__)
+#else
+#define VPRINTF(...) __nothing
+#endif
+
extern int _end[];
extern int KERNEL_BASE_phys[];
extern int KERNEL_BASE_virt[];
@@ -77,12 +85,6 @@ char *boot_args = NULL;
/* filled in before cleaning bss. keep in .data */
u_int uboot_args[4] __attribute__((__section__(".data")));
-/*
- * Macros to translate between physical and virtual for a subset of the
- * kernel address space. *Not* for general use.
- */
-#define KERN_VTOPDIFF ((vaddr_t)KERNEL_BASE_phys - (vaddr_t)KERNEL_BASE_virt)
-
#ifndef CONADDR
#define CONADDR (IMX7_AIPS_BASE + AIPS3_UART1_BASE)
#endif
@@ -96,11 +98,31 @@ u_int uboot_args[4] __attribute__((__sec
void imx7_setup_iomux(void);
void imx7_setup_gpio(void);
void imx7board_device_register(device_t, void *);
+void imx7_mpstart(void);
+void imx7_platform_early_putchar(char);
#ifdef KGDB
#include <sys/kgdb.h>
#endif
+static void
+earlyconsputc(dev_t dev, int c)
+{
+ uartputc(c);
+}
+
+static int
+earlyconsgetc(dev_t dev)
+{
+ return 0;
+}
+
+static struct consdev earlycons = {
+ .cn_putc = earlyconsputc,
+ .cn_getc = earlyconsgetc,
+ .cn_pollc = nullcnpollc,
+};
+
/*
* Static device mappings. These peripheral registers are mapped at
* fixed virtual addresses very early in initarm() so that we can use
@@ -142,6 +164,74 @@ static struct boot_physmem bp_highgig =
};
#endif
+void
+imx7_platform_early_putchar(char c)
+{
+#define CONADDR_VA (CONADDR - IMX7_IOREG_PBASE + KERNEL_IO_IOREG_VBASE)
+ volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ?
+ (volatile uint32_t *)CONADDR_VA :
+ (volatile uint32_t *)CONADDR;
+
+ int timo = 150000;
+
+ while ((uartaddr[IMX_USR2 / 4] & IMX_USR2_TXDC) == 0) {
+ if (--timo == 0)
+ break;
+ }
+
+ uartaddr[IMX_UTXD / 4] = c;
+
+ timo = 150000;
+ while ((uartaddr[IMX_USR2 / 4] & IMX_USR2_TXDC) == 0) {
+ if (--timo == 0)
+ break;
+ }
+}
+
+void
+imx7_mpstart(void)
+{
+#if defined(MULTIPROCESSOR)
+ if (arm_cpu_max <= 1)
+ return;
+
+ const bus_space_tag_t bst = &armv7_generic_bs_tag;
+
+ const bus_space_handle_t bsh = KERNEL_IO_IOREG_VBASE + AIPS1_SRC_BASE;
+ const paddr_t mpstart = KERN_VTOPHYS((vaddr_t)cpu_mpstart);
+
+ bus_space_write_4(bst, bsh, SRC_GPR3, mpstart);
+
+ uint32_t rcr1 = bus_space_read_4(bst, bsh, SRC_A7RCR1);
+ rcr1 |= SRC_A7RCR1_A7_CORE1_ENABLE;
+ bus_space_write_4(bst, bsh, SRC_A7RCR1, rcr1);
+
+ arm_dsb();
+ __asm __volatile("sev" ::: "memory");
+
+ for (int loop = 0; loop < 16; loop++) {
+ VPRINTF("%u hatched %#x\n", loop, arm_cpu_hatched);
+ if (arm_cpu_hatched == __BITS(arm_cpu_max - 1, 1))
+ break;
+ int timo = 1500000;
+ while (arm_cpu_hatched != __BITS(arm_cpu_max - 1, 1))
+ if (--timo == 0)
+ break;
+ }
+ for (size_t i = 1; i < arm_cpu_max; i++) {
+ if ((arm_cpu_hatched & __BIT(i)) == 0) {
+ printf("%s: warning: cpu%zu failed to hatch\n",
+ __func__, i);
+ }
+ }
+
+ VPRINTF(" (%u cpu%s, hatched %#x)",
+ arm_cpu_max, arm_cpu_max ? "s" : "",
+ arm_cpu_hatched);
+#endif
+}
+
+
/*
* u_int initarm(...)
*
@@ -159,9 +249,17 @@ initarm(void *arg)
{
psize_t memsize;
- kern_vtopdiff = KERN_VTOPDIFF;
+ /*
+ * Heads up ... Setup the CPU / MMU / TLB functions
+ */
+ if (set_cpufuncs()) // starts PMC counter
+ panic("cpu not recognized!");
+
+ cn_tab = &earlycons;
+
+ extern char ARM_BOOTSTRAP_LxPT[];
+ pmap_devmap_bootstrap((vaddr_t)ARM_BOOTSTRAP_LxPT, devmap);
- pmap_devmap_register(devmap);
imx7_bootstrap(KERNEL_IO_IOREG_VBASE);
imx7_setup_iomux();
@@ -169,12 +267,6 @@ initarm(void *arg)
consinit();
- /*
- * Heads up ... Setup the CPU / MMU / TLB functions
- */
- if (set_cpufuncs()) // starts PMC counter
- panic("cpu not recognized!");
-
cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
#ifdef NO_POWERSAVE
@@ -266,7 +358,14 @@ initarm(void *arg)
&bp_highgig, 1);
}
#endif
- return initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0);
+ u_int sp = initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0);
+
+ /*
+ * initarm_common flushes cache if required before AP start
+ */
+ imx7_mpstart();
+
+ return sp;
}
#ifdef CONSDEVNAME
Index: src/sys/arch/evbarm/kobo/kobo_machdep.c
diff -u src/sys/arch/evbarm/kobo/kobo_machdep.c:1.5 src/sys/arch/evbarm/kobo/kobo_machdep.c:1.6
--- src/sys/arch/evbarm/kobo/kobo_machdep.c:1.5 Fri Sep 21 12:04:09 2018
+++ src/sys/arch/evbarm/kobo/kobo_machdep.c Sat May 18 08:49:24 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: kobo_machdep.c,v 1.5 2018/09/21 12:04:09 skrll Exp $ */
+/* $NetBSD: kobo_machdep.c,v 1.6 2019/05/18 08:49:24 skrll Exp $ */
/*
* Copyright (c) 2002, 2003, 2005, 2010 Genetec Corporation.
@@ -102,7 +102,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: kobo_machdep.c,v 1.5 2018/09/21 12:04:09 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: kobo_machdep.c,v 1.6 2019/05/18 08:49:24 skrll Exp $");
#include "opt_evbarm_boardtype.h"
#include "opt_arm_debug.h"
@@ -151,6 +151,9 @@ char *boot_args = NULL;
extern char KERNEL_BASE_phys[];
+/* filled in before cleaning bss. keep in .data */
+u_int uboot_args[4] __attribute__((__section__(".data")));
+
/*
* Macros to translate between physical and virtual for a subset of the
* kernel address space. *Not* for general use.
@@ -428,14 +431,11 @@ initarm(void *arg)
if (set_cpufuncs()) // starts PMC counter
panic("cpu not recognized!");
- /* map some peripheral registers */
- pmap_devmap_bootstrap((vaddr_t)armreg_ttbr_read() & -L1_TABLE_SIZE,
- kobo_devmap);
+ extern char ARM_BOOTSTRAP_LxPT[];
+ pmap_devmap_bootstrap((vaddr_t)ARM_BOOTSTRAP_LxPT, kobo_devmap);
cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
- /* Register devmap for devices we mapped in start */
- pmap_devmap_register(kobo_devmap);
setup_ioports();
consinit();
Index: src/sys/arch/evbarm/netwalker/netwalker_start.S
diff -u src/sys/arch/evbarm/netwalker/netwalker_start.S:1.5 src/sys/arch/evbarm/netwalker/netwalker_start.S:1.6
--- src/sys/arch/evbarm/netwalker/netwalker_start.S:1.5 Tue May 6 11:22:53 2014
+++ src/sys/arch/evbarm/netwalker/netwalker_start.S Sat May 18 08:49:24 2019
@@ -1,4 +1,33 @@
-/* $NetBSD: netwalker_start.S,v 1.5 2014/05/06 11:22:53 hkenken Exp $ */
+/* $NetBSD: netwalker_start.S,v 1.6 2019/05/18 08:49:24 skrll Exp $ */
+
+/*-
+ * Copyright (c) 2012 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
/*-
* Copyright (c) 2009 SHIMIZU Ryo <r...@nerv.org>
@@ -66,7 +95,7 @@
#include <arm/imx/imxuartreg.h>
#include <evbarm/netwalker/netwalker_reg.h>
-RCSID("$NetBSD: netwalker_start.S,v 1.5 2014/05/06 11:22:53 hkenken Exp $")
+RCSID("$NetBSD: netwalker_start.S,v 1.6 2019/05/18 08:49:24 skrll Exp $")
#if defined(VERBOSE_INIT_ARM)
#define DEBUG_STARTUP
@@ -230,7 +259,391 @@ relocated:
.Lrelocate_address:
.word KERNEL_BASE_phys
-#include <arm/cortex/a9_mpsubr.S>
+#include "opt_console.h"
+#include "opt_cpuoptions.h"
+#include "opt_cputypes.h"
+#include "opt_multiprocessor.h"
+
+#include <arm/asm.h>
+#include <arm/armreg.h>
+#include <arm/cortex/scu_reg.h>
+#include "assym.h"
+
+// Macro to call routines in .text
+#if defined(KERNEL_BASES_EQUAL)
+#define CALL(f) bl _C_LABEL(f)
+#else
+#define CALL(f) \
+ movw fp, #:lower16:_C_LABEL(f); \
+ movt fp, #:upper16:_C_LABEL(f); \
+ sub fp, fp, #KERNEL_BASE_VOFFSET; \
+ blx fp
+#endif
+
+
+// We'll modify va and pa at run time so we can use relocatable addresses.
+#define MMU_INIT(va,pa,n_sec,attr) \
+ .word ((va) & 0xffffffff)|(n_sec) ; \
+ .word ((pa) & 0xffffffff)|(attr) ; \
+
+// Set up a preliminary mapping in the MMU to allow us to run at KERNEL_BASE
+// with caches on. If we are MULTIPROCESSOR, save the TTB address.
+//
+arm_boot_l1pt_init:
+
+ mov ip, r1 // save mmu table addr
+ // Build page table from scratch
+ mov r1, r0 // Start address to clear memory.
+ // Zero the entire table so all virtual addresses are invalid.
+ add r2, r1, #L1_TABLE_SIZE // Ending address
+ mov r4, #0
+ mov r5, #0
+ mov r6, #0
+ mov r7, #0
+1: stmia r1!, {r4-r7} // 16 bytes at a time
+ cmp r1, r2
+ blt 1b
+
+ // Now create our entries per the mmu_init_table.
+ l1table .req r0
+ va .req r1
+ pa .req r2
+ n_sec .req r3
+ attr .req r4
+ itable .req r5
+
+ mov attr, #0
+ mrc p15, 0, r3, c0, c0, 5 // MPIDR read
+ cmp r3, #0 // not zero?
+ movne attr, #L1_S_V6_S // yes, shareable attribute
+ mov itable, ip // reclaim table address
+ b 3f
+
+2: str pa, [l1table, va, lsl #2]
+ add va, va, #1
+ add pa, pa, #(L1_S_SIZE)
+ subs n_sec, n_sec, #1
+ bhi 2b
+
+3: ldmia itable!, {va, pa}
+ // Convert va to l1 offset: va = 4 * (va >> L1_S_SHIFT)
+ ubfx n_sec, va, #0, #L1_S_SHIFT
+ lsr va, va, #L1_S_SHIFT
+
+ // Do we need add sharing for this?
+ tst pa, #(L1_S_C|L1_S_B) // is this entry cacheable?
+ orrne pa, pa, attr // add sharing
+
+4: cmp n_sec, #0
+ bne 2b
+ bx lr // return
+
+ .unreq va
+ .unreq pa
+ .unreq n_sec
+ .unreq attr
+ .unreq itable
+ .unreq l1table
+
+//
+// Coprocessor register initialization values
+//
+#undef CPU_CONTROL_SWP_ENABLE // not present on A8
+#define CPU_CONTROL_SWP_ENABLE 0
+#ifdef __ARMEL__
+#define CPU_CONTROL_EX_BEND_SET 0
+#else
+#define CPU_CONTROL_EX_BEND_SET CPU_CONTROL_EX_BEND
+#endif
+#ifdef ARM32_DISABLE_ALIGNMENT_FAULTS
+#define CPU_CONTROL_AFLT_ENABLE_CLR CPU_CONTROL_AFLT_ENABLE
+#define CPU_CONTROL_AFLT_ENABLE_SET 0
+#else
+#define CPU_CONTROL_AFLT_ENABLE_CLR 0
+#define CPU_CONTROL_AFLT_ENABLE_SET CPU_CONTROL_AFLT_ENABLE
+#endif
+
+// bits to set in the Control Register
+//
+#define CPU_CONTROL_SET \
+ (CPU_CONTROL_MMU_ENABLE | \
+ CPU_CONTROL_AFLT_ENABLE_SET | \
+ CPU_CONTROL_DC_ENABLE | \
+ CPU_CONTROL_SWP_ENABLE | \
+ CPU_CONTROL_BPRD_ENABLE | \
+ CPU_CONTROL_IC_ENABLE | \
+ CPU_CONTROL_EX_BEND_SET | \
+ CPU_CONTROL_UNAL_ENABLE)
+
+// bits to clear in the Control Register
+//
+#define CPU_CONTROL_CLR \
+ (CPU_CONTROL_AFLT_ENABLE_CLR | \
+ CPU_CONTROL_TR_ENABLE)
+
+arm_cpuinit:
+ // Because the MMU may already be on do a typical sequence to set
+ // the Translation Table Base(s).
+ mov ip, lr
+ mov r10, r0 // save TTBR
+ mov r1, #0
+
+ mcr p15, 0, r1, c7, c5, 0 // invalidate I cache
+
+ mrc p15, 0, r2, c1, c0, 0 // SCTLR read
+ movw r1, #(CPU_CONTROL_DC_ENABLE|CPU_CONTROL_IC_ENABLE)
+ bic r2, r2, r1 // clear I+D cache enable
+
+#ifdef __ARMEB__
+ // SCTLR.EE determines the endianness of translation table lookups.
+ // So we need to make sure it's set before starting to use the new
+ // translation tables (which are big endian).
+ //
+ orr r2, r2, #CPU_CONTROL_EX_BEND
+ bic r2, r2, #CPU_CONTROL_MMU_ENABLE
+ pli [pc, #32] // preload the next few cachelines
+ pli [pc, #64]
+ pli [pc, #96]
+ pli [pc, #128]
+#endif
+
+ mcr p15, 0, r2, c1, c0, 0 // SCTLR write
+
+ XPUTC(#'F')
+ dsb // Drain the write buffers.
+
+ XPUTC(#'G')
+ mrc p15, 0, r1, c0, c0, 5 // MPIDR read
+ cmp r1, #0
+ orrlt r10, r10, #TTBR_MPATTR // MP, cachable (Normal WB)
+ orrge r10, r10, #TTBR_UPATTR // Non-MP, cacheable, normal WB
+ XPUTC(#'0')
+ mcr p15, 0, r10, c2, c0, 0 // TTBR0 write
+#if defined(ARM_MMU_EXTENDED)
+ // When using split TTBRs, we need to set both since the physical
+ // addresses we were/are using might be in either.
+ XPUTC(#'1')
+ mcr p15, 0, r10, c2, c0, 1 // TTBR1 write
+#endif
+
+ XPUTC(#'H')
+#if defined(ARM_MMU_EXTENDED)
+ XPUTC(#'1')
+ mov r1, #TTBCR_S_N_1 // make sure TTBCR_S_N is 1
+#else
+ XPUTC(#'0')
+ mov r1, #0 // make sure TTBCR is 0
+#endif
+ mcr p15, 0, r1, c2, c0, 2 // TTBCR write
+
+ isb
+
+ XPUTC(#'I')
+ mov r1, #0
+ mcr p15, 0, r1, c8, c7, 0 // TLBIALL (just this core)
+ dsb
+ isb
+
+ XPUTC(#'J')
+ mov r1, #0 // get KERNEL_PID
+ mcr p15, 0, r1, c13, c0, 1 // CONTEXTIDR write
+
+ // Set the Domain Access register. Very important!
+ XPUTC(#'K')
+ mov r1, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
+ mcr p15, 0, r1, c3, c0, 0 // DACR write
+
+ //
+ // Enable the MMU, etc.
+ //
+ XPUTC(#'L')
+ mrc p15, 0, r1, c1, c0, 0 // SCTLR read
+
+ movw r3, #:lower16:CPU_CONTROL_SET
+#if (CPU_CONTROL_SET & 0xffff0000)
+ movt r3, #:upper16:CPU_CONTROL_SET
+#endif
+ orr r0, r1, r3
+ bic r0, r0, #CPU_CONTROL_CLR
+ //cmp r0, r1 // any changes to SCTLR?
+ //bxeq ip // no, then return.
+
+ pli 1f
+ dsb
+
+ // turn mmu on!
+ //
+ mov r0, r0 // fetch instruction cacheline
+1: mcr p15, 0, r0, c1, c0, 0 // SCTLR write
+
+ // Ensure that the coprocessor has finished turning on the MMU.
+ //
+ mrc p15, 0, r0, c0, c0, 0 // Read an arbitrary value.
+ mov r0, r0 // Stall until read completes.
+ XPUTC(#'M')
+
+ bx ip // return
+
+ .p2align 2
+
+#if defined(VERBOSE_INIT_ARM) && defined(XPUTC_COM)
+#define TIMO 0x25000
+#ifndef COM_MULT
+#define COM_MULT 1
+#endif
+xputc:
+ mov r2, #TIMO
+#ifdef CONADDR
+ movw r3, #:lower16:CONADDR
+ movt r3, #:upper16:CONADDR
+#elif defined(CONSADDR)
+ movw r3, #:lower16:CONSADDR
+ movt r3, #:upper16:CONSADDR
+#endif
+1:
+#if COM_MULT == 1
+ ldrb r1, [r3, #(COM_LSR*COM_MULT)]
+#else
+#if COM_MULT == 2
+ ldrh r1, [r3, #(COM_LSR*COM_MULT)]
+#elif COM_MULT == 4
+ ldr r1, [r3, #(COM_LSR*COM_MULT)]
+#endif
+#ifdef COM_BSWAP
+ lsr r1, r1, #(COM_MULT-1)*8
+#endif
+#endif
+ tst r1, #LSR_TXRDY
+ bne 2f
+ subs r2, r2, #1
+ bne 1b
+2:
+#if COM_MULT == 1
+ strb r0, [r3, #COM_DATA]
+#else
+#ifdef COM_BSWAP
+ lsl r0, r0, #(COM_MULT-1)*8
+#endif
+#if COM_MULT == 2
+ strh r0, [r3, #COM_DATA]
+#else
+ str r0, [r3, #COM_DATA]
+#endif
+#endif
+
+ mov r2, #TIMO
+3:
+#if COM_MULT == 1
+ ldrb r1, [r3, #(COM_LSR*COM_MULT)]
+#else
+#if COM_MULT == 2
+ ldrh r1, [r3, #(COM_LSR*COM_MULT)]
+#elif COM_MULT == 4
+ ldr r1, [r3, #(COM_LSR*COM_MULT)]
+#endif
+#ifdef COM_BSWAP
+ lsr r1, r1, #(COM_MULT-1)*8
+#endif
+#endif
+ tst r1, #LSR_TSRE
+ bne 4f
+ subs r2, r2, #1
+ bne 3b
+4:
+ bx lr
+#endif /* VERBOSE_INIT_ARM */
+
+//
+// Perform the initialization of the Cortex core required by NetBSD.
+//
+//
+cortex_init:
+ mov r10, lr // save lr
+ mov r9, sp // save sp
+
+
+1:
+ cpsid if, #PSR_SVC32_MODE // SVC32 with no interrupts
+
+2:
+ mov r0, #0
+ msr spsr_sxc, r0 // set SPSR[23:8] to known value
+
+ mov sp, r9 // restore sp
+
+#if 0
+ mrc p14, 0, r0, c0, c0, 0 // MIDR read
+ ufbx r0, r0, #4, #4 // extract cortex part.
+ mov r5, #1
+ lsl r5, r5, r0
+#endif
+
+ XPUTC(#'@')
+
+ mrc p15, 0, r4, c1, c0, 0 // SCTLR read
+
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 // toss i-cache
+
+
+ //
+ // Step 1b, invalidate the data cache
+ //
+ XPUTC(#'B')
+ CALL(armv7_dcache_wbinv_all)
+ XPUTC(#'C')
+
+ //
+ // Check to see if we are really MP before enabling SMP mode
+ //
+ mrc p15, 0, r1, c0, c0, 5 // MPIDR get
+ ubfx r1, r1, #30, #2 // get MP bits
+ cmp r1, #2 // is it MP?
+ bxne r10 // no, return
+
+ //
+ // Step 2, disable the data cache
+ //
+ mrc p15, 0, r2, c1, c0, 0 // SCTLR read
+ bic r2, r2, #CPU_CONTROL_DC_ENABLE // clear data cache enable
+ mcr p15, 0, r2, c1, c0, 0 // SCTLR write
+ isb
+ XPUTC(#'1')
+
+ //
+ // Step 4b, restore SCTLR (enable the data cache)
+ //
+ orr r4, r4, #CPU_CONTROL_IC_ENABLE // enable icache
+ orr r4, r4, #CPU_CONTROL_DC_ENABLE // enable dcache
+ mcr p15, 0, r4, c1, c0, 0 // SCTLR write
+ isb
+ XPUTC(#'-')
+
+ bx r10
+ASEND(cortex_init)
+
+
+ .global cortex_mpstart
+ .type cortex_mpstart,%object
+
+#ifdef VERBOSE_INIT_ARM
+ .pushsection .bss
+ /* temporary stack for secondary CPUs (for XPUTC) */
+#define BOOT_STACKSIZE 256
+ .align 3
+ .space BOOT_STACKSIZE * (MAXCPUS - 1)
+bootstk_cpus:
+ .popsection
+#endif
+
+cortex_mpstart:
+ //
+ // If not MULTIPROCESSOR, drop CPU into power saving state.
+ //
+3: wfi
+ b 3b
+ASEND(cortex_mpstart)
+
.Lmmu_init_table:
/* fill all table VA==PA */
