Module Name: src
Committed By: msaitoh
Date: Wed Jul 24 14:57:09 UTC 2019
Modified Files:
src/sys/external/bsd/drm2/dist/drm/i915: i915_drv.h i915_reg.h
intel_pm.c intel_uncore.c
Log Message:
Use unsigned. Found by KUBSan.
To generate a diff of this commit:
cvs rdiff -u -r1.28 -r1.29 src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h
cvs rdiff -u -r1.5 -r1.6 src/sys/external/bsd/drm2/dist/drm/i915/i915_reg.h
cvs rdiff -u -r1.16 -r1.17 src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c
cvs rdiff -u -r1.10 -r1.11 \
src/sys/external/bsd/drm2/dist/drm/i915/intel_uncore.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h
diff -u src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h:1.28 src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h:1.29
--- src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h:1.28 Thu Sep 13 08:25:55 2018
+++ src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h Wed Jul 24 14:57:09 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: i915_drv.h,v 1.28 2018/09/13 08:25:55 mrg Exp $ */
+/* $NetBSD: i915_drv.h,v 1.29 2019/07/24 14:57:09 msaitoh Exp $ */
/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
*/
@@ -1424,7 +1424,7 @@ struct i915_gpu_error {
atomic_t reset_counter;
#define I915_RESET_IN_PROGRESS_FLAG 1
-#define I915_WEDGED (1 << 31)
+#define I915_WEDGED (1UL << 31)
/**
* Waitqueue to signal when the reset has completed. Used by clients
Index: src/sys/external/bsd/drm2/dist/drm/i915/i915_reg.h
diff -u src/sys/external/bsd/drm2/dist/drm/i915/i915_reg.h:1.5 src/sys/external/bsd/drm2/dist/drm/i915/i915_reg.h:1.6
--- src/sys/external/bsd/drm2/dist/drm/i915/i915_reg.h:1.5 Thu Sep 13 08:25:55 2018
+++ src/sys/external/bsd/drm2/dist/drm/i915/i915_reg.h Wed Jul 24 14:57:09 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: i915_reg.h,v 1.5 2018/09/13 08:25:55 mrg Exp $ */
+/* $NetBSD: i915_reg.h,v 1.6 2019/07/24 14:57:09 msaitoh Exp $ */
/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
@@ -184,7 +184,7 @@
#define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
#define GEN6_STOLEN_RESERVED 0x1082C0
-#define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
+#define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFFUL << 20)
#define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
#define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
#define GEN6_STOLEN_RESERVED_1M (0 << 4)
@@ -1660,7 +1660,7 @@ enum skl_disp_power_wells {
#define GEN8_FAULT_TLB_DATA1 0x04b14
#define FPGA_DBG 0x42300
-#define FPGA_DBG_RM_NOCLAIM (1<<31)
+#define FPGA_DBG_RM_NOCLAIM (1UL << 31)
#define DERRMR 0x44050
/* Note that HBLANK events are reserved on bdw+ */
@@ -1721,7 +1721,7 @@ enum skl_disp_power_wells {
#define GFX_MODE 0x02520
#define GFX_MODE_GEN7 0x0229c
#define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
-#define GFX_RUN_LIST_ENABLE (1<<15)
+#define GFX_RUN_LIST_ENABLE (1U << 15)
#define GFX_INTERRUPT_STEERING (1<<14)
#define GFX_TLB_INVALIDATE_EXPLICIT (1<<13)
#define GFX_SURFACE_FAULT_ENABLE (1<<12)
@@ -2065,7 +2065,7 @@ enum skl_disp_power_wells {
/* Framebuffer compression for GM45+ */
#define DPFC_CB_BASE 0x3200
#define DPFC_CONTROL 0x3208
-#define DPFC_CTL_EN (1<<31)
+#define DPFC_CTL_EN (1UL << 31)
#define DPFC_CTL_PLANE(plane) ((plane)<<30)
#define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29)
#define DPFC_CTL_FENCE_EN (1<<29)
@@ -2175,7 +2175,7 @@ enum skl_disp_power_wells {
#define GMBUS_PIN_3_BXT 3
#define GMBUS_NUM_PINS 7 /* including 0 */
#define GMBUS1 (dev_priv->gpio_mmio_base + 0x5104) /* command/status */
-#define GMBUS_SW_CLR_INT (1<<31)
+#define GMBUS_SW_CLR_INT (1UL << 31)
#define GMBUS_SW_RDY (1<<30)
#define GMBUS_ENT (1<<29) /* enable timeout */
#define GMBUS_CYCLE_NONE (0<<25)
@@ -3507,7 +3507,7 @@ enum skl_disp_power_wells {
/* Panel power sequencing */
#define PP_STATUS 0x61200
-#define PP_ON (1 << 31)
+#define PP_ON (1UL << 31)
/*
* Indicates that all dependencies of the panel are on:
*
@@ -4279,7 +4279,7 @@ enum skl_disp_power_wells {
#define DPD_AUX_CH_DATA4 0x64320
#define DPD_AUX_CH_DATA5 0x64324
-#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
+#define DP_AUX_CH_CTL_SEND_BUSY (1UL << 31)
#define DP_AUX_CH_CTL_DONE (1 << 30)
#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
@@ -4366,7 +4366,7 @@ enum skl_disp_power_wells {
#define DSL_LINEMASK_GEN2 0x00000fff
#define DSL_LINEMASK_GEN3 0x00001fff
#define _PIPEACONF 0x70008
-#define PIPECONF_ENABLE (1<<31)
+#define PIPECONF_ENABLE (1UL << 31)
#define PIPECONF_DISABLE 0
#define PIPECONF_DOUBLE_WIDE (1<<30)
#define I965_PIPECONF_ACTIVE (1<<30)
@@ -4794,7 +4794,7 @@ enum skl_disp_power_wells {
/* define the Watermark register on Ironlake */
#define WM0_PIPEA_ILK 0x45100
-#define WM0_PIPE_PLANE_MASK (0xffff<<16)
+#define WM0_PIPE_PLANE_MASK (0xffffUL << 16)
#define WM0_PIPE_PLANE_SHIFT 16
#define WM0_PIPE_SPRITE_MASK (0xff<<8)
#define WM0_PIPE_SPRITE_SHIFT 8
@@ -4803,7 +4803,7 @@ enum skl_disp_power_wells {
#define WM0_PIPEB_ILK 0x45104
#define WM0_PIPEC_IVB 0x45200
#define WM1_LP_ILK 0x45108
-#define WM1_LP_SR_EN (1<<31)
+#define WM1_LP_SR_EN (1UL << 31)
#define WM1_LP_LATENCY_SHIFT 24
#define WM1_LP_LATENCY_MASK (0x7f<<24)
#define WM1_LP_FBC_MASK (0xf<<20)
@@ -4931,7 +4931,7 @@ enum skl_disp_power_wells {
/* Display A control */
#define _DSPACNTR 0x70180
-#define DISPLAY_PLANE_ENABLE (1<<31)
+#define DISPLAY_PLANE_ENABLE (1UL << 31)
#define DISPLAY_PLANE_DISABLE 0
#define DISPPLANE_GAMMA_ENABLE (1<<30)
#define DISPPLANE_GAMMA_DISABLE 0
@@ -5119,7 +5119,7 @@ enum skl_disp_power_wells {
#define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
#define _SPRA_CTL 0x70280
-#define SPRITE_ENABLE (1<<31)
+#define SPRITE_ENABLE (1UL << 31)
#define SPRITE_GAMMA_ENABLE (1<<30)
#define SPRITE_PIXFORMAT_MASK (7<<25)
#define SPRITE_FORMAT_YUV422 (0<<25)
@@ -5551,7 +5551,7 @@ enum skl_disp_power_wells {
/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
#define _PFA_CTL_1 0x68080
#define _PFB_CTL_1 0x68880
-#define PF_ENABLE (1<<31)
+#define PF_ENABLE (1UL << 31)
#define PF_PIPE_SEL_MASK_IVB (3<<29)
#define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
#define PF_FILTER_MASK (3<<23)
@@ -5716,7 +5716,7 @@ enum skl_disp_power_wells {
#define GAMMA_MODE_MODE_SPLIT (3 << 0)
/* interrupts */
-#define DE_MASTER_IRQ_CONTROL (1 << 31)
+#define DE_MASTER_IRQ_CONTROL (1UL << 31)
#define DE_SPRITEB_FLIP_DONE (1 << 29)
#define DE_SPRITEA_FLIP_DONE (1 << 28)
#define DE_PLANEB_FLIP_DONE (1 << 27)
@@ -5780,7 +5780,7 @@ enum skl_disp_power_wells {
#define GTIER 0x4401c
#define GEN8_MASTER_IRQ 0x44200
-#define GEN8_MASTER_IRQ_CONTROL (1<<31)
+#define GEN8_MASTER_IRQ_CONTROL (1UL << 31)
#define GEN8_PCU_IRQ (1<<30)
#define GEN8_DE_PCH_IRQ (1<<23)
#define GEN8_DE_MISC_IRQ (1<<22)
@@ -5812,7 +5812,7 @@ enum skl_disp_power_wells {
#define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe)))
#define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe)))
#define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe)))
-#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
+#define GEN8_PIPE_FIFO_UNDERRUN (1UL << 31)
#define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
#define GEN8_PIPE_CURSOR_FAULT (1 << 10)
@@ -6042,7 +6042,7 @@ enum skl_disp_power_wells {
#define SDE_AUDIO_POWER_C_CPT (1 << 30)
#define SDE_AUDIO_POWER_B_CPT (1 << 29)
#define SDE_AUDIO_POWER_SHIFT_CPT 29
-#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
+#define SDE_AUDIO_POWER_MASK_CPT (7UL << 29)
#define SDE_AUXD_CPT (1 << 27)
#define SDE_AUXC_CPT (1 << 26)
#define SDE_AUXB_CPT (1 << 25)
@@ -6572,8 +6572,8 @@ enum skl_disp_power_wells {
#define PCH_PP_STATUS 0xc7200
#define PCH_PP_CONTROL 0xc7204
-#define PANEL_UNLOCK_REGS (0xabcd << 16)
-#define PANEL_UNLOCK_MASK (0xffff << 16)
+#define PANEL_UNLOCK_REGS (0xabcdUL << 16)
+#define PANEL_UNLOCK_MASK (0xffffUL << 16)
#define BXT_POWER_CYCLE_DELAY_MASK (0x1f0)
#define BXT_POWER_CYCLE_DELAY_SHIFT 4
#define EDP_FORCE_VDD (1 << 3)
@@ -6805,7 +6805,7 @@ enum skl_disp_power_wells {
#define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24)
#define GEN7_RC_CTL_TO_MODE (1<<28)
#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
-#define GEN6_RC_CTL_HW_ENABLE (1<<31)
+#define GEN6_RC_CTL_HW_ENABLE (1UL << 31)
#define GEN6_RP_DOWN_TIMEOUT 0xA010
#define GEN6_RP_INTERRUPT_LIMITS 0xA014
#define GEN6_RPSTAT1 0xA01C
@@ -6860,7 +6860,7 @@ enum skl_disp_power_wells {
#define VLV_RCEDATA 0xA0BC
#define GEN6_RC6pp_THRESHOLD 0xA0C0
#define GEN6_PMINTRMSK 0xA168
-#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31)
+#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1UL <<31)
#define VLV_PWRDWNUPCTL 0xA294
#define GEN9_MEDIA_PG_IDLE_HYSTERESIS 0xA0C4
#define GEN9_RENDER_PG_IDLE_HYSTERESIS 0xA0C8
@@ -6911,7 +6911,7 @@ enum skl_disp_power_wells {
#define VLV_MEDIA_C0_COUNT 0x13811C
#define GEN6_PCODE_MAILBOX 0x138124
-#define GEN6_PCODE_READY (1<<31)
+#define GEN6_PCODE_READY (1UL << 31)
#define GEN6_PCODE_WRITE_RC6VIDS 0x4
#define GEN6_PCODE_READ_RC6VIDS 0x5
#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
@@ -7181,7 +7181,7 @@ enum skl_disp_power_wells {
#define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */
#define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */
#define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */
-#define HSW_PWR_WELL_ENABLE_REQUEST (1<<31)
+#define HSW_PWR_WELL_ENABLE_REQUEST (1UL << 31)
#define HSW_PWR_WELL_STATE_ENABLED (1<<30)
#define HSW_PWR_WELL_CTL5 0x45410
#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
@@ -7203,7 +7203,7 @@ enum skl_disp_power_wells {
#define TRANS_DDI_FUNC_CTL_EDP 0x6F400
#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A)
-#define TRANS_DDI_FUNC_ENABLE (1<<31)
+#define TRANS_DDI_FUNC_ENABLE (1UL << 31)
/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
#define TRANS_DDI_PORT_MASK (7<<28)
#define TRANS_DDI_PORT_SHIFT 28
@@ -7234,7 +7234,7 @@ enum skl_disp_power_wells {
#define DP_TP_CTL_A 0x64040
#define DP_TP_CTL_B 0x64140
#define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
-#define DP_TP_CTL_ENABLE (1<<31)
+#define DP_TP_CTL_ENABLE (1UL << 31)
#define DP_TP_CTL_MODE_SST (0<<27)
#define DP_TP_CTL_MODE_MST (1<<27)
#define DP_TP_CTL_FORCE_ACT (1<<25)
@@ -7264,7 +7264,7 @@ enum skl_disp_power_wells {
#define DDI_BUF_CTL_A 0x64000
#define DDI_BUF_CTL_B 0x64100
#define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
-#define DDI_BUF_CTL_ENABLE (1<<31)
+#define DDI_BUF_CTL_ENABLE (1UL << 31)
#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
#define DDI_BUF_EMP_MASK (0xf<<24)
#define DDI_BUF_PORT_REVERSAL (1<<16)
@@ -7323,7 +7323,7 @@ enum skl_disp_power_wells {
/* SPLL */
#define SPLL_CTL 0x46020
-#define SPLL_PLL_ENABLE (1<<31)
+#define SPLL_PLL_ENABLE (1UL << 31)
#define SPLL_PLL_SSC (1<<28)
#define SPLL_PLL_NON_SSC (2<<28)
#define SPLL_PLL_LCPLL (3<<28)
@@ -7337,7 +7337,7 @@ enum skl_disp_power_wells {
#define WRPLL_CTL1 0x46040
#define WRPLL_CTL2 0x46060
#define WRPLL_CTL(pll) (pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2)
-#define WRPLL_PLL_ENABLE (1<<31)
+#define WRPLL_PLL_ENABLE (1UL << 31)
#define WRPLL_PLL_SSC (1<<28)
#define WRPLL_PLL_NON_SSC (2<<28)
#define WRPLL_PLL_LCPLL (3<<28)
@@ -7360,7 +7360,7 @@ enum skl_disp_power_wells {
#define PORT_CLK_SEL_LCPLL_1350 (1<<29)
#define PORT_CLK_SEL_LCPLL_810 (2<<29)
#define PORT_CLK_SEL_SPLL (3<<29)
-#define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29)
+#define PORT_CLK_SEL_WRPLL(pll) (((u32)(pll)+4)<<29)
#define PORT_CLK_SEL_WRPLL1 (4U<<29)
#define PORT_CLK_SEL_WRPLL2 (5U<<29)
#define PORT_CLK_SEL_NONE (7U<<29)
@@ -7391,7 +7391,7 @@ enum skl_disp_power_wells {
/* LCPLL Control */
#define LCPLL_CTL 0x130040
-#define LCPLL_PLL_DISABLE (1<<31)
+#define LCPLL_PLL_DISABLE (1UL << 31)
#define LCPLL_PLL_LOCK (1<<30)
#define LCPLL_CLK_FREQ_MASK (3<<26)
#define LCPLL_CLK_FREQ_450 (0<<26)
Index: src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c
diff -u src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c:1.16 src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c:1.17
--- src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c:1.16 Thu Sep 13 08:25:55 2018
+++ src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c Wed Jul 24 14:57:09 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: intel_pm.c,v 1.16 2018/09/13 08:25:55 mrg Exp $ */
+/* $NetBSD: intel_pm.c,v 1.17 2019/07/24 14:57:09 msaitoh Exp $ */
/*
* Copyright © 2012 Intel Corporation
@@ -28,7 +28,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intel_pm.c,v 1.16 2018/09/13 08:25:55 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intel_pm.c,v 1.17 2019/07/24 14:57:09 msaitoh Exp $");
#include <linux/bitops.h>
#include <linux/cpufreq.h>
@@ -4625,7 +4625,7 @@ static void gen6_disable_rps(struct drm_
struct drm_i915_private *dev_priv = dev->dev_private;
I915_WRITE(GEN6_RC_CONTROL, 0);
- I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
+ I915_WRITE(GEN6_RPNSWREQ, 1UL << 31);
}
static void cherryview_disable_rps(struct drm_device *dev)
Index: src/sys/external/bsd/drm2/dist/drm/i915/intel_uncore.c
diff -u src/sys/external/bsd/drm2/dist/drm/i915/intel_uncore.c:1.10 src/sys/external/bsd/drm2/dist/drm/i915/intel_uncore.c:1.11
--- src/sys/external/bsd/drm2/dist/drm/i915/intel_uncore.c:1.10 Mon Aug 27 15:09:35 2018
+++ src/sys/external/bsd/drm2/dist/drm/i915/intel_uncore.c Wed Jul 24 14:57:09 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: intel_uncore.c,v 1.10 2018/08/27 15:09:35 riastradh Exp $ */
+/* $NetBSD: intel_uncore.c,v 1.11 2019/07/24 14:57:09 msaitoh Exp $ */
/*
* Copyright © 2013 Intel Corporation
@@ -24,7 +24,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intel_uncore.c,v 1.10 2018/08/27 15:09:35 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intel_uncore.c,v 1.11 2019/07/24 14:57:09 msaitoh Exp $");
#include "i915_drv.h"
#include "intel_drv.h"
@@ -1109,7 +1109,7 @@ static void fw_domain_init(struct drm_i9
d->val_clear = 0;
} else {
/* WaRsClearFWBitsAtReset:bdw,skl */
- d->val_reset = _MASKED_BIT_DISABLE(0xffff);
+ d->val_reset = _MASKED_BIT_DISABLE(0xffffU);
d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
}
