Module Name: src
Committed By: jmcneill
Date: Mon Oct 28 22:21:35 UTC 2019
Modified Files:
src/sys/arch/arm/ti: am3_prcm.c files.ti
Added Files:
src/sys/arch/arm/ti: ti_gpio.c
Log Message:
Add support for GPIO controller.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/ti/am3_prcm.c
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/ti/files.ti
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/ti/ti_gpio.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/ti/am3_prcm.c
diff -u src/sys/arch/arm/ti/am3_prcm.c:1.5 src/sys/arch/arm/ti/am3_prcm.c:1.6
--- src/sys/arch/arm/ti/am3_prcm.c:1.5 Mon Oct 28 21:16:10 2019
+++ src/sys/arch/arm/ti/am3_prcm.c Mon Oct 28 22:21:35 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: am3_prcm.c,v 1.5 2019/10/28 21:16:10 jmcneill Exp $ */
+/* $NetBSD: am3_prcm.c,v 1.6 2019/10/28 22:21:35 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca>
@@ -28,7 +28,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: am3_prcm.c,v 1.5 2019/10/28 21:16:10 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: am3_prcm.c,v 1.6 2019/10/28 22:21:35 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -101,6 +101,11 @@ static struct ti_prcm_clk am3_prcm_clks[
AM3_PRCM_HWMOD_PER("i2c2", 0x48, "PERIPH_CLK"),
AM3_PRCM_HWMOD_PER("i2c3", 0x44, "PERIPH_CLK"),
+ AM3_PRCM_HWMOD_WKUP("gpio1", 0x8, "PERIPH_CLK"),
+ AM3_PRCM_HWMOD_PER("gpio2", 0xac, "PERIPH_CLK"),
+ AM3_PRCM_HWMOD_PER("gpio3", 0xb0, "PERIPH_CLK"),
+ AM3_PRCM_HWMOD_PER("gpio4", 0xb4, "PERIPH_CLK"),
+
AM3_PRCM_HWMOD_WKUP("timer0", 0x10, "FIXED_32K"),
AM3_PRCM_HWMOD_PER("timer2", 0x80, "PERIPH_CLK"),
AM3_PRCM_HWMOD_PER("timer3", 0x84, "PERIPH_CLK"),
Index: src/sys/arch/arm/ti/files.ti
diff -u src/sys/arch/arm/ti/files.ti:1.12 src/sys/arch/arm/ti/files.ti:1.13
--- src/sys/arch/arm/ti/files.ti:1.12 Mon Oct 28 21:16:47 2019
+++ src/sys/arch/arm/ti/files.ti Mon Oct 28 22:21:35 2019
@@ -1,4 +1,4 @@
-# $NetBSD: files.ti,v 1.12 2019/10/28 21:16:47 jmcneill Exp $
+# $NetBSD: files.ti,v 1.13 2019/10/28 22:21:35 jmcneill Exp $
#
file arch/arm/ti/ti_platform.c soc_ti
@@ -45,6 +45,11 @@ device omaptimer
attach omaptimer at fdt
file arch/arm/ti/ti_omaptimer.c omaptimer
+# GPIO
+device tigpio: gpiobus
+attach tigpio at fdt with ti_gpio
+file arch/arm/ti/ti_gpio.c ti_gpio
+
# I2C
device tiiic: i2cbus, i2cexec
attach tiiic at fdt with ti_iic
Added files:
Index: src/sys/arch/arm/ti/ti_gpio.c
diff -u /dev/null src/sys/arch/arm/ti/ti_gpio.c:1.1
--- /dev/null Mon Oct 28 22:21:35 2019
+++ src/sys/arch/arm/ti/ti_gpio.c Mon Oct 28 22:21:35 2019
@@ -0,0 +1,302 @@
+/* $NetBSD: ti_gpio.c,v 1.1 2019/10/28 22:21:35 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2019 Jared McNeill <jmcne...@invisible.ca>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: ti_gpio.c,v 1.1 2019/10/28 22:21:35 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/mutex.h>
+#include <sys/kmem.h>
+#include <sys/gpio.h>
+#include <sys/bitops.h>
+
+#include <dev/fdt/fdtvar.h>
+#include <dev/gpio/gpiovar.h>
+
+#include <arm/ti/ti_prcm.h>
+
+#define GPIO_OE 0x134
+#define GPIO_DATAIN 0x138
+#define GPIO_CLEARDATAOUT 0x190
+#define GPIO_SETDATAOUT 0x194
+
+static const char * const compatible[] = {
+ "ti,omap4-gpio",
+ NULL
+};
+
+struct ti_gpio_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+ kmutex_t sc_lock;
+
+ struct gpio_chipset_tag sc_gp;
+ gpio_pin_t sc_pins[32];
+ device_t sc_gpiodev;
+};
+
+struct ti_gpio_pin {
+ struct ti_gpio_softc *pin_sc;
+ u_int pin_nr;
+ int pin_flags;
+ bool pin_actlo;
+};
+
+#define RD4(sc, reg) \
+ bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
+#define WR4(sc, reg, val) \
+ bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
+
+static int ti_gpio_match(device_t, cfdata_t, void *);
+static void ti_gpio_attach(device_t, device_t, void *);
+
+CFATTACH_DECL_NEW(ti_gpio, sizeof(struct ti_gpio_softc),
+ ti_gpio_match, ti_gpio_attach, NULL, NULL);
+
+static int
+ti_gpio_ctl(struct ti_gpio_softc *sc, u_int pin, int flags)
+{
+ uint32_t oe;
+
+ KASSERT(mutex_owned(&sc->sc_lock));
+
+ oe = RD4(sc, GPIO_OE);
+ if (flags & GPIO_PIN_INPUT)
+ oe |= __BIT(pin);
+ else if (flags & GPIO_PIN_OUTPUT)
+ oe &= ~__BIT(pin);
+ WR4(sc, GPIO_OE, oe);
+
+ return 0;
+}
+
+static void *
+ti_gpio_acquire(device_t dev, const void *data, size_t len, int flags)
+{
+ struct ti_gpio_softc * const sc = device_private(dev);
+ struct ti_gpio_pin *gpin;
+ const u_int *gpio = data;
+ int error;
+
+ if (len != 12)
+ return NULL;
+
+ const uint8_t pin = be32toh(gpio[1]) & 0xff;
+ const bool actlo = be32toh(gpio[2]) & 1;
+
+ if (pin >= __arraycount(sc->sc_pins))
+ return NULL;
+
+ mutex_enter(&sc->sc_lock);
+ error = ti_gpio_ctl(sc, pin, flags);
+ mutex_exit(&sc->sc_lock);
+
+ if (error != 0)
+ return NULL;
+
+ gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP);
+ gpin->pin_sc = sc;
+ gpin->pin_nr = pin;
+ gpin->pin_flags = flags;
+ gpin->pin_actlo = actlo;
+
+ return gpin;
+}
+
+static void
+ti_gpio_release(device_t dev, void *priv)
+{
+ struct ti_gpio_softc * const sc = device_private(dev);
+ struct ti_gpio_pin *pin = priv;
+
+ mutex_enter(&sc->sc_lock);
+ ti_gpio_ctl(pin->pin_sc, pin->pin_nr, GPIO_PIN_INPUT);
+ mutex_exit(&sc->sc_lock);
+
+ kmem_free(pin, sizeof(*pin));
+}
+
+static int
+ti_gpio_read(device_t dev, void *priv, bool raw)
+{
+ struct ti_gpio_softc * const sc = device_private(dev);
+ struct ti_gpio_pin *pin = priv;
+ uint32_t data;
+ int val;
+
+ KASSERT(sc == pin->pin_sc);
+
+ const uint32_t data_mask = __BIT(pin->pin_nr);
+
+ /* No lock required for reads */
+ data = RD4(sc, GPIO_DATAIN);
+ val = __SHIFTOUT(data, data_mask);
+ if (!raw && pin->pin_actlo)
+ val = !val;
+
+ return val;
+}
+
+static void
+ti_gpio_write(device_t dev, void *priv, int val, bool raw)
+{
+ struct ti_gpio_softc * const sc = device_private(dev);
+ struct ti_gpio_pin *pin = priv;
+
+ KASSERT(sc == pin->pin_sc);
+
+ const uint32_t data_mask = __BIT(pin->pin_nr);
+
+ if (!raw && pin->pin_actlo)
+ val = !val;
+
+ const u_int data_reg = val ? GPIO_SETDATAOUT : GPIO_CLEARDATAOUT;
+
+ WR4(sc, data_reg, data_mask);
+}
+
+static struct fdtbus_gpio_controller_func ti_gpio_funcs = {
+ .acquire = ti_gpio_acquire,
+ .release = ti_gpio_release,
+ .read = ti_gpio_read,
+ .write = ti_gpio_write,
+};
+
+static int
+ti_gpio_pin_read(void *priv, int pin)
+{
+ struct ti_gpio_softc * const sc = priv;
+ uint32_t data;
+ int val;
+
+ KASSERT(pin < __arraycount(sc->sc_pins));
+
+ const uint32_t data_mask = __BIT(pin);
+
+ data = RD4(sc, GPIO_DATAIN);
+ val = __SHIFTOUT(data, data_mask);
+
+ return val;
+}
+
+static void
+ti_gpio_pin_write(void *priv, int pin, int val)
+{
+ struct ti_gpio_softc * const sc = priv;
+
+ KASSERT(pin < __arraycount(sc->sc_pins));
+
+ const u_int data_reg = val ? GPIO_SETDATAOUT : GPIO_CLEARDATAOUT;
+ const uint32_t data_mask = __BIT(pin);
+
+ WR4(sc, data_reg, data_mask);
+}
+
+static void
+ti_gpio_pin_ctl(void *priv, int pin, int flags)
+{
+ struct ti_gpio_softc * const sc = priv;
+
+ KASSERT(pin < __arraycount(sc->sc_pins));
+
+ mutex_enter(&sc->sc_lock);
+ ti_gpio_ctl(sc, pin, flags);
+ mutex_exit(&sc->sc_lock);
+}
+
+static void
+ti_gpio_attach_ports(struct ti_gpio_softc *sc)
+{
+ struct gpio_chipset_tag *gp = &sc->sc_gp;
+ struct gpiobus_attach_args gba;
+ u_int pin;
+
+ gp->gp_cookie = sc;
+ gp->gp_pin_read = ti_gpio_pin_read;
+ gp->gp_pin_write = ti_gpio_pin_write;
+ gp->gp_pin_ctl = ti_gpio_pin_ctl;
+
+ for (pin = 0; pin < __arraycount(sc->sc_pins); pin++) {
+ sc->sc_pins[pin].pin_num = pin;
+ sc->sc_pins[pin].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT;
+ sc->sc_pins[pin].pin_state = ti_gpio_pin_read(sc, pin);
+ }
+
+ memset(&gba, 0, sizeof(gba));
+ gba.gba_gc = gp;
+ gba.gba_pins = sc->sc_pins;
+ gba.gba_npins = __arraycount(sc->sc_pins);
+ sc->sc_gpiodev = config_found_ia(sc->sc_dev, "gpiobus", &gba, NULL);
+}
+
+static int
+ti_gpio_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct fdt_attach_args * const faa = aux;
+
+ return of_match_compatible(faa->faa_phandle, compatible);
+}
+
+static void
+ti_gpio_attach(device_t parent, device_t self, void *aux)
+{
+ struct ti_gpio_softc * const sc = device_private(self);
+ struct fdt_attach_args * const faa = aux;
+ const int phandle = faa->faa_phandle;
+ bus_addr_t addr;
+ bus_size_t size;
+
+ if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
+ aprint_error(": couldn't get registers\n");
+ return;
+ }
+ if (ti_prcm_enable_hwmod(OF_parent(phandle), 0) != 0) {
+ aprint_error(": couldn't enable module\n");
+ return;
+ }
+
+ sc->sc_dev = self;
+ sc->sc_bst = faa->faa_bst;
+ if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
+ aprint_error(": couldn't map registers\n");
+ return;
+ }
+ mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
+
+ aprint_naive("\n");
+ aprint_normal(": GPIO (%s)\n", fdtbus_get_string(OF_parent(phandle), "ti,hwmods"));
+
+ fdtbus_register_gpio_controller(self, phandle, &ti_gpio_funcs);
+
+ ti_gpio_attach_ports(sc);
+}
