Module Name: src
Committed By: msaitoh
Date: Fri Nov 15 12:38:09 UTC 2019
Modified Files:
src/sys/dev/pci: if_msk.c if_skreg.h
Log Message:
Make Yukon EX, FE+, SUPR stable. The code is mainly taken from FreeBSD.
At least, this change made my own Yukon EX machine (HP ProBook 4501s) much
stable than before.
To generate a diff of this commit:
cvs rdiff -u -r1.93 -r1.94 src/sys/dev/pci/if_msk.c
cvs rdiff -u -r1.26 -r1.27 src/sys/dev/pci/if_skreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/if_msk.c
diff -u src/sys/dev/pci/if_msk.c:1.93 src/sys/dev/pci/if_msk.c:1.94
--- src/sys/dev/pci/if_msk.c:1.93 Sun Nov 10 21:16:36 2019
+++ src/sys/dev/pci/if_msk.c Fri Nov 15 12:38:09 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: if_msk.c,v 1.93 2019/11/10 21:16:36 chs Exp $ */
+/* $NetBSD: if_msk.c,v 1.94 2019/11/15 12:38:09 msaitoh Exp $ */
/* $OpenBSD: if_msk.c,v 1.79 2009/10/15 17:54:56 deraadt Exp $ */
/*
@@ -52,7 +52,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.93 2019/11/10 21:16:36 chs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_msk.c,v 1.94 2019/11/15 12:38:09 msaitoh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -881,10 +881,27 @@ void
mskc_reset(struct sk_softc *sc)
{
uint32_t imtimer_ticks, reg1;
+ uint16_t status;
int reg;
DPRINTFN(2, ("mskc_reset\n"));
+ /* Disable ASF */
+ if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_SUPR)) {
+ CSR_WRITE_4(sc, SK_Y2_CPU_WDOG, 0);
+ status = CSR_READ_2(sc, SK_Y2_ASF_HCU_CCSR);
+ /* Clear AHB bridge & microcontroller reset. */
+ status &= ~(SK_Y2_ASF_HCU_CSSR_ARB_RST |
+ SK_Y2_ASF_HCU_CSSR_CPU_RST_MODE);
+ /* Clear ASF microcontroller state. */
+ status &= ~SK_Y2_ASF_HCU_CSSR_UC_STATE_MSK;
+ status &= ~SK_Y2_ASF_HCU_CSSR_CPU_CLK_DIVIDE_MSK;
+ CSR_WRITE_2(sc, SK_Y2_ASF_HCU_CCSR, status);
+ CSR_WRITE_4(sc, SK_Y2_CPU_WDOG, 0);
+ } else
+ CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET);
+ CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF);
+
CSR_WRITE_1(sc, SK_CSR, SK_CSR_SW_RESET);
CSR_WRITE_1(sc, SK_CSR, SK_CSR_MASTER_RESET);
@@ -957,10 +974,6 @@ mskc_reset(struct sk_softc *sc)
DPRINTFN(2, ("mskc_reset: sk_link_ctrl=%x\n",
CSR_READ_2(sc, SK_LINK_CTRL)));
- /* Disable ASF */
- CSR_WRITE_1(sc, SK_Y2_ASF_CSR, SK_Y2_ASF_RESET);
- CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF);
-
/* Clear I2C IRQ noise */
CSR_WRITE_4(sc, SK_I2CHWIRQ, 1);
@@ -1096,9 +1109,9 @@ msk_reset(struct sk_if_softc *sc_if)
{
/* GMAC and GPHY Reset */
SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
- SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
+ SK_IF_WRITE_1(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
DELAY(1000);
- SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR);
+ SK_IF_WRITE_1(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_CLEAR);
SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
}
@@ -2404,17 +2417,31 @@ msk_init_yukon(struct sk_if_softc *sc_if
/* Configure RX MAC FIFO */
SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
- SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON |
- SK_RFCTL_FIFO_FLUSH_ON);
-
- /* Increase flush threshold to 64 bytes */
- SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
- SK_RFCTL_FIFO_THRESHOLD + 1);
+ v = SK_RFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
+ if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_FE_P))
+ v |= SK_RFCTL_RX_OVER_ON;
+ SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
+
+ if ((sc->sk_type == SK_YUKON_FE_P) &&
+ (sc->sk_rev == SK_YUKON_FE_P_REV_A0))
+ v = 0x178; /* Magic value */
+ else {
+ /* Increase flush threshold to 64 bytes */
+ v = SK_RFCTL_FIFO_THRESHOLD + 1;
+ }
+ SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD, v);
/* Configure TX MAC FIFO */
SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
+ if ((sc->sk_type == SK_YUKON_FE_P) &&
+ (sc->sk_rev == SK_YUKON_FE_P_REV_A0)) {
+ v = SK_IF_READ_2(sc_if, 0, SK_TXMF1_END);
+ v &= ~SK_TXEND_WM_ON;
+ SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_END, v);
+ }
+
#if 1
SK_YU_WRITE_2(sc_if, YUKON_GPCR, YU_GPCR_TXEN | YU_GPCR_RXEN);
#endif
@@ -2451,7 +2478,7 @@ msk_init(struct ifnet *ifp)
/* Configure transmit arbiter(s) */
SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_ON);
#if 0
- SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON);
+/* SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON); */
#endif
if (sc->sk_ramsize) {
@@ -2559,6 +2586,13 @@ msk_init(struct ifnet *ifp)
SK_IF_WRITE_2(sc_if, 0, SK_RXQ1_Y2_PREF_PUTIDX,
sc_if->sk_cdata.sk_rx_prod);
+
+ if ((sc->sk_type == SK_YUKON_EX) || (sc->sk_type == SK_YUKON_SUPR)) {
+ /* Disable flushing of non-ASF packets. */
+ SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST,
+ SK_RFCTL_RX_MACSEC_FLUSH_OFF);
+ }
+
/* Configure interrupt handling */
if (sc_if->sk_port == SK_PORT_A)
sc->sk_intrmask |= SK_Y2_INTRS1;
Index: src/sys/dev/pci/if_skreg.h
diff -u src/sys/dev/pci/if_skreg.h:1.26 src/sys/dev/pci/if_skreg.h:1.27
--- src/sys/dev/pci/if_skreg.h:1.26 Tue Mar 5 08:25:02 2019
+++ src/sys/dev/pci/if_skreg.h Fri Nov 15 12:38:09 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: if_skreg.h,v 1.26 2019/03/05 08:25:02 msaitoh Exp $ */
+/* $NetBSD: if_skreg.h,v 1.27 2019/11/15 12:38:09 msaitoh Exp $ */
/*-
* Copyright (c) 2003 The NetBSD Foundation, Inc.
@@ -1112,7 +1112,11 @@
#define SK_RXMF1_READ_LEVEL 0x0C78
/* Receive MAC FIFO 1 Control/Test */
-#define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/
+#define SK_RFCTL_RX_MACSEC_FLUSH_ON 0x00800000
+#define SK_RFCTL_RX_MACSEC_FLUSH_OFF 0x00400000
+#define SK_RFCTL_RX_OVER_ON 0x00080000 /* Flush on RX Overrun on */
+#define SK_RFCTL_RX_OVER_OFF 0x00040000 /* Flush on RX Overrun off */
+#define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on */
#define SK_RFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */
#define SK_RFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */
#define SK_RFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */
@@ -1199,6 +1203,9 @@
#define SK_TXMF1_RESTART_PTR 0x0D74
#define SK_TXMF1_READ_LEVEL 0x0D78
+/* Transmit MAC FIFO End Address */
+#define SK_TXEND_WM_ON 0x00000003 /* ??? */
+
/* Transmit MAC FIFO Control/Test */
#define SK_TFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/
#define SK_TFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */
@@ -1275,10 +1282,17 @@
#define SK_TSTAMP_STOP 0x02
#define SK_TSTAMP_START 0x04
-#define SK_Y2_ASF_CSR 0x0e68
+#define SK_Y2_CPU_WDOG 0x0e48
+#define SK_Y2_ASF_CSR 0x0e68
#define SK_Y2_ASF_RESET 0x08
+#define SK_Y2_ASF_HCU_CCSR 0x0e68
+#define SK_Y2_ASF_HCU_CSSR_ARB_RST __BIT(9)
+#define SK_Y2_ASF_HCU_CSSR_CPU_RST_MODE __BIT(8)
+#define SK_Y2_ASF_HCU_CSSR_CPU_CLK_DIVIDE_MSK __BITS(4, 3)
+#define SK_Y2_ASF_HCU_CSSR_UC_STATE_MSK __BITS(1, 0)
+
#define SK_Y2_LEV_ITIMERINIT 0x0eb0
#define SK_Y2_LEV_ITIMERCTL 0x0eb8
#define SK_Y2_TX_ITIMERINIT 0x0ec0
