Module Name: src
Committed By: skrll
Date: Thu Sep 23 06:34:00 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: cpufunc.c
src/sys/arch/arm/arm32: cpu.c
Log Message:
Print the cache information in similar formats and arm and aarch64, e.g.
arm before
[ 1.0000000] cpu0: 32KB/64B 2-way L1 PIPT Instruction cache
[ 1.0000000] cpu0: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache
[ 1.0000000] cpu0: 2304KB/64B 16-way write-through L2 PIPT Unified cache
arm after
[ 1.0000000] cpu0: L1 32KB/64B 2-way (256 set) PIPT Instruction cache
[ 1.0000000] cpu0: L1 32KB/64B 2-way (256 set) write-back-locking-C PIPT Data
cache
[ 1.0000000] cpu0: L2 2304KB/64B 16-way (2304 set) write-through PIPT Unified
cache
aarch64 before
[ 1.0000030] cpu1: L1 48KB/64B*256L*3W PIPT Instruction cache
[ 1.0000030] cpu1: L1 32KB/64B*256L*2W PIPT Data cache
[ 1.0000030] cpu1: L2 2048KB/64B*2048L*16W PIPT Unified cache
aarch64 after
[ 1.0000030] cpu1: L1 48KB/64B 3-way (256 set) PIPT Instruction cache
[ 1.0000030] cpu1: L1 32KB/64B 2-way (256 set) PIPT Data cache
[ 1.0000030] cpu1: L2 2048KB/64B 16-way (2048 set) PIPT Unified cache
To generate a diff of this commit:
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/aarch64/aarch64/cpufunc.c
cvs rdiff -u -r1.148 -r1.149 src/sys/arch/arm/arm32/cpu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/cpufunc.c
diff -u src/sys/arch/aarch64/aarch64/cpufunc.c:1.27 src/sys/arch/aarch64/aarch64/cpufunc.c:1.28
--- src/sys/arch/aarch64/aarch64/cpufunc.c:1.27 Mon Jan 11 17:12:13 2021
+++ src/sys/arch/aarch64/aarch64/cpufunc.c Thu Sep 23 06:34:00 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.27 2021/01/11 17:12:13 skrll Exp $ */
+/* $NetBSD: cpufunc.c,v 1.28 2021/09/23 06:34:00 skrll Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu <r...@nerv.org>
@@ -30,7 +30,7 @@
#include "opt_multiprocessor.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.27 2021/01/11 17:12:13 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.28 2021/09/23 06:34:00 skrll Exp $");
#include <sys/param.h>
#include <sys/types.h>
@@ -295,12 +295,12 @@ prt_cache(device_t self, struct aarch64_
}
aprint_verbose_dev(self,
- "L%d %uKB/%uB*%uL*%uW %s %s cache\n",
+ "L%d %uKB/%uB %u-way (%u set) %s %s cache\n",
level + 1,
cunit->cache_size / 1024,
cunit->cache_line_size,
- cunit->cache_sets,
cunit->cache_ways,
+ cunit->cache_sets,
cachetype, cacheable);
if (cinfo[level].cacheable != CACHE_CACHEABLE_IDCACHE)
Index: src/sys/arch/arm/arm32/cpu.c
diff -u src/sys/arch/arm/arm32/cpu.c:1.148 src/sys/arch/arm/arm32/cpu.c:1.149
--- src/sys/arch/arm/arm32/cpu.c:1.148 Tue Jul 6 08:34:28 2021
+++ src/sys/arch/arm/arm32/cpu.c Thu Sep 23 06:34:00 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.148 2021/07/06 08:34:28 skrll Exp $ */
+/* $NetBSD: cpu.c,v 1.149 2021/09/23 06:34:00 skrll Exp $ */
/*
* Copyright (c) 1995 Mark Brinicombe.
@@ -46,7 +46,7 @@
#include "opt_multiprocessor.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.148 2021/07/06 08:34:28 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.149 2021/09/23 06:34:00 skrll Exp $");
#include <sys/param.h>
@@ -608,22 +608,28 @@ static void
print_cache_info(device_t dv, struct arm_cache_info *info, u_int level)
{
if (info->cache_unified) {
- aprint_normal_dev(dv, "%dKB/%dB %d-way %s L%u %cI%cT Unified cache\n",
+ aprint_normal_dev(dv, "L%u %dKB/%dB %d-way (%u set) %s %cI%cT Unified cache\n",
+ level + 1,
info->dcache_size / 1024,
info->dcache_line_size, info->dcache_ways,
- wtnames[info->cache_type], level + 1,
+ info->dcache_sets,
+ wtnames[info->cache_type],
info->dcache_type & CACHE_TYPE_PIxx ? 'P' : 'V',
info->dcache_type & CACHE_TYPE_xxPT ? 'P' : 'V');
} else {
- aprint_normal_dev(dv, "%dKB/%dB %d-way L%u %cI%cT Instruction cache\n",
+ aprint_normal_dev(dv, "L%u %dKB/%dB %d-way (%u set) %cI%cT Instruction cache\n",
+ level + 1,
info->icache_size / 1024,
- info->icache_line_size, info->icache_ways, level + 1,
+ info->icache_line_size, info->icache_ways,
+ info->icache_sets,
info->icache_type & CACHE_TYPE_PIxx ? 'P' : 'V',
info->icache_type & CACHE_TYPE_xxPT ? 'P' : 'V');
- aprint_normal_dev(dv, "%dKB/%dB %d-way %s L%u %cI%cT Data cache\n",
+ aprint_normal_dev(dv, "L%u %dKB/%dB %d-way (%u set) %s %cI%cT Data cache\n",
+ level + 1,
info->dcache_size / 1024,
info->dcache_line_size, info->dcache_ways,
- wtnames[info->cache_type], level + 1,
+ info->dcache_sets,
+ wtnames[info->cache_type],
info->dcache_type & CACHE_TYPE_PIxx ? 'P' : 'V',
info->dcache_type & CACHE_TYPE_xxPT ? 'P' : 'V');
}
