Module Name: src
Committed By: skrll
Date: Thu Sep 30 21:19:16 UTC 2021
Modified Files:
src/sys/arch/aarch64/aarch64: genassym.cf locore.S pmap.c
Log Message:
Ensure TCR_EPD0 is set on entry to pmap_activate and ensure it is set as
early as possible for APs.
To generate a diff of this commit:
cvs rdiff -u -r1.34 -r1.35 src/sys/arch/aarch64/aarch64/genassym.cf
cvs rdiff -u -r1.79 -r1.80 src/sys/arch/aarch64/aarch64/locore.S
cvs rdiff -u -r1.115 -r1.116 src/sys/arch/aarch64/aarch64/pmap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/genassym.cf
diff -u src/sys/arch/aarch64/aarch64/genassym.cf:1.34 src/sys/arch/aarch64/aarch64/genassym.cf:1.35
--- src/sys/arch/aarch64/aarch64/genassym.cf:1.34 Sat Sep 18 12:25:06 2021
+++ src/sys/arch/aarch64/aarch64/genassym.cf Thu Sep 30 21:19:16 2021
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.34 2021/09/18 12:25:06 jmcneill Exp $
+# $NetBSD: genassym.cf,v 1.35 2021/09/30 21:19:16 skrll Exp $
#-
# Copyright (c) 2014 The NetBSD Foundation, Inc.
# All rights reserved.
@@ -137,6 +137,7 @@ define TCR_IRGN0_NC TCR_IRGN0_NC
define TCR_IRGN0_WB_WA TCR_IRGN0_WB_WA
define TCR_IRGN0_WT TCR_IRGN0_WT
define TCR_IRGN0_WB TCR_IRGN0_WB
+define TCR_EPD0 TCR_EPD0
define TCR_T0SZ TCR_T0SZ
define EFAULT EFAULT
Index: src/sys/arch/aarch64/aarch64/locore.S
diff -u src/sys/arch/aarch64/aarch64/locore.S:1.79 src/sys/arch/aarch64/aarch64/locore.S:1.80
--- src/sys/arch/aarch64/aarch64/locore.S:1.79 Mon Aug 30 22:24:39 2021
+++ src/sys/arch/aarch64/aarch64/locore.S Thu Sep 30 21:19:16 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.79 2021/08/30 22:24:39 jmcneill Exp $ */
+/* $NetBSD: locore.S,v 1.80 2021/09/30 21:19:16 skrll Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu <r...@nerv.org>
@@ -38,7 +38,7 @@
#include <aarch64/hypervisor.h>
#include "assym.h"
-RCSID("$NetBSD: locore.S,v 1.79 2021/08/30 22:24:39 jmcneill Exp $")
+RCSID("$NetBSD: locore.S,v 1.80 2021/09/30 21:19:16 skrll Exp $")
#ifdef AARCH64_DEVICE_MEM_STRONGLY_ORDERED
#define MAIR_DEVICE_MEM MAIR_DEVICE_nGnRnE
@@ -468,7 +468,27 @@ ENTRY_NP(cpu_mpstart)
mp_vstart:
hint 0x24 /* bti j */
+
CPU_DPRINTREG("PC = ", x20)
+ CPU_DPRINTREG("SP = ", sp)
+
+ CPU_DPRINTSREG("TTBR0 = ", ttbr0_el1)
+ CPU_DPRINTSREG("TTBR1 = ", ttbr1_el1)
+
+ /* Set SP to VA */
+ adrl x0, kern_vtopdiff
+ ldr x0, [x0]
+ add sp, sp, x0
+
+ /* stop using TTBR0 - CPU_DPRINT{,REG,SREG} no longer after this */
+ mrs x0, tcr_el1
+ orr x0, x0, #TCR_EPD0
+ msr tcr_el1, x0
+ isb
+
+ tlbi vmalle1is
+ dsb ish
+ isb
/* set exception vector */
adrl x0, _C_LABEL(el1_vectors)
Index: src/sys/arch/aarch64/aarch64/pmap.c
diff -u src/sys/arch/aarch64/aarch64/pmap.c:1.115 src/sys/arch/aarch64/aarch64/pmap.c:1.116
--- src/sys/arch/aarch64/aarch64/pmap.c:1.115 Sun Sep 26 09:58:13 2021
+++ src/sys/arch/aarch64/aarch64/pmap.c Thu Sep 30 21:19:16 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.115 2021/09/26 09:58:13 skrll Exp $ */
+/* $NetBSD: pmap.c,v 1.116 2021/09/30 21:19:16 skrll Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu <r...@nerv.org>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.115 2021/09/26 09:58:13 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.116 2021/09/30 21:19:16 skrll Exp $");
#include "opt_arm_debug.h"
#include "opt_ddb.h"
@@ -1426,6 +1426,8 @@ pmap_activate(struct lwp *l)
UVMHIST_CALLARGS(pmaphist, "lwp=%p asid=%d (pid=%d)", l, pm->pm_asid,
l->l_proc->p_pid, 0);
+ KASSERT((reg_tcr_el1_read() & TCR_EPD0) != 0);
+
if (pm == pmap_kernel())
return;
if (l != curlwp)
