Module Name: src Committed By: jmcneill Date: Sun Nov 7 16:57:40 UTC 2021
Modified Files: src/sys/external/gpl2/dts/dist/arch/arm/boot/dts: bcm2835-common.dtsi bcm2835-rpi-zero-w.dts bcm2835-rpi.dtsi bcm283x.dtsi src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/allwinner: sun50i-h5-nanopi-neo-plus2.dts sun50i-h6-pine-h64.dts sun50i-h6.dtsi src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic: Makefile meson-gx.dtsi meson-gxbb.dtsi meson-gxl.dtsi src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/arm: vexpress-v2m-rs1.dtsi src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/rockchip: rk3328-rock64.dts src/sys/external/gpl2/dts/dist/include/dt-bindings/clock: sun50i-h6-r-ccu.h src/sys/external/gpl2/dts/dist/include/dt-bindings/input: linux-event-codes.h src/sys/external/gpl2/dts/dist/include/dt-bindings/reset: sun50i-h6-r-ccu.h Added Files: src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic: meson-g12b-odroid-n2-plus.dts Removed Files: src/sys/external/gpl2/dts/dist/arch/arm/boot/dts: at91-kizboxmini.dts atlas6-evb.dts atlas6.dtsi atlas7-evb.dts atlas7.dtsi efm32gg-dk3750.dts efm32gg.dtsi imx6q-dhcom-som.dtsi mt8135-pinfunc.h picoxcell-pc3x2.dtsi picoxcell-pc3x3.dtsi picoxcell-pc7302-pc3x2.dts picoxcell-pc7302-pc3x3.dts prima2-evb.dts prima2.dtsi ste-href-ab8505.dtsi ste-href-tvk1281618.dtsi ste-u300.dts stm32h743-pinctrl.dtsi stm32mp157-pinctrl.dtsi stm32mp157c.dtsi stm32mp157xaa-pinctrl.dtsi stm32mp157xab-pinctrl.dtsi stm32mp157xac-pinctrl.dtsi stm32mp157xad-pinctrl.dtsi tango4-common.dtsi tango4-smp8758.dtsi tango4-vantage-1172.dts zx296702-ad1.dts zx296702.dtsi src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/al: Makefile alpine-v2-evp.dts alpine-v2.dtsi src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray: stingray-sata.dtsi src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek: mt8183-pinfunc.h src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/qcom: apq8016-sbc-pmic-pins.dtsi apq8016-sbc-soc-pins.dtsi apq8096-db820c-pins.dtsi apq8096-db820c-pmic-pins.dtsi msm8992-pins.dtsi msm8994-pins.dtsi msm8994-smd-rpm.dtsi msm8996-pins.dtsi msm8998-pins.dtsi src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas: r8a7795-es1-h3ulcb-kf.dts r8a7795-es1-h3ulcb.dts r8a7795-es1-salvator-x.dts r8a7795-es1.dtsi r8a7795-h3ulcb-kf.dts r8a7795-h3ulcb.dts r8a7795-salvator-x.dts r8a7795-salvator-xs.dts r8a7795.dtsi r8a7796-m3ulcb-kf.dts r8a7796-m3ulcb.dts r8a7796-salvator-x.dts r8a7796-salvator-xs.dts r8a7796.dtsi r8a77965-m3nulcb-kf.dts r8a77965-m3nulcb.dts src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/rockchip: rk3399-rock-pi-4.dts src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/xilinx: zynqmp-clk.dtsi src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/zte: Makefile zx296718-evb.dts zx296718-pcbox.dts zx296718.dtsi src/sys/external/gpl2/dts/dist/include/dt-bindings/clk: ti-dra7-atl.h src/sys/external/gpl2/dts/dist/include/dt-bindings/clock: zx296702-clock.h zx296718-clock.h src/sys/external/gpl2/dts/dist/include/dt-bindings/soc: zte,pm_domains.h Log Message: Merge conflicts. To generate a diff of this commit: cvs rdiff -u -r1.1.1.5 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/at91-kizboxmini.dts \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/stm32mp157c.dtsi cvs rdiff -u -r1.1.1.3 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/atlas6-evb.dts \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/atlas6.dtsi \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/atlas7-evb.dts \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/atlas7.dtsi \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/efm32gg-dk3750.dts \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/imx6q-dhcom-som.dtsi \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/prima2-evb.dts \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/prima2.dtsi \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ste-href-tvk1281618.dtsi \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/tango4-common.dtsi \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/tango4-smp8758.dtsi \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/tango4-vantage-1172.dts cvs rdiff -u -r1.3 -r1.4 \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/bcm2835-common.dtsi cvs rdiff -u -r1.2 -r1.3 \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts cvs rdiff -u -r1.7 -r1.8 \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/bcm2835-rpi.dtsi cvs rdiff -u -r1.9 -r1.10 \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/bcm283x.dtsi cvs rdiff -u -r1.1.1.2 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/efm32gg.dtsi \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/mt8135-pinfunc.h \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ste-href-ab8505.dtsi cvs rdiff -u -r1.1.1.4 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/picoxcell-pc3x2.dtsi \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/picoxcell-pc3x3.dtsi \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ste-u300.dts \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/zx296702-ad1.dts \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/zx296702.dtsi cvs rdiff -u -r1.1.1.7 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/stm32h743-pinctrl.dtsi cvs rdiff -u -r1.1.1.1 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/stm32mp157xaa-pinctrl.dtsi \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/stm32mp157xab-pinctrl.dtsi \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/stm32mp157xac-pinctrl.dtsi \ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/stm32mp157xad-pinctrl.dtsi cvs rdiff -u -r1.1.1.3 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/al/Makefile cvs rdiff -u -r1.1.1.1 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/al/alpine-v2-evp.dts cvs rdiff -u -r1.1.1.2 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/al/alpine-v2.dtsi cvs rdiff -u -r1.3 -r1.4 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts cvs rdiff -u -r1.7 -r1.8 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi cvs rdiff -u -r1.3 -r1.4 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/Makefile cvs rdiff -u -r0 -r1.3 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts cvs rdiff -u -r1.4 -r1.5 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/meson-gx.dtsi \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi cvs rdiff -u -r1.6 -r1.7 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi cvs rdiff -u -r1.1.1.3 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi cvs rdiff -u -r1.1.1.1 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h cvs rdiff -u -r1.1.1.3 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi cvs rdiff -u -r1.1.1.2 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/qcom/msm8994-pins.dtsi \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/qcom/msm8994-smd-rpm.dtsi \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/qcom/msm8998-pins.dtsi cvs rdiff -u -r1.1.1.5 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi cvs rdiff -u -r1.1.1.4 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi cvs rdiff -u -r1.1.1.2 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts cvs rdiff -u -r1.1.1.6 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts cvs rdiff -u -r1.1.1.7 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts cvs rdiff -u -r1.1.1.4 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts cvs rdiff -u -r1.1.1.8 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts cvs rdiff -u -r1.1.1.9 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/r8a7795.dtsi \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/r8a7796.dtsi cvs rdiff -u -r1.1.1.5 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts cvs rdiff -u -r1.1.1.1 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/r8a77965-m3nulcb-kf.dts \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/r8a77965-m3nulcb.dts cvs rdiff -u -r1.4 -r1.5 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts cvs rdiff -u -r1.1.1.2 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts cvs rdiff -u -r1.1.1.2 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi cvs rdiff -u -r1.1.1.4 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/zte/Makefile \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/zte/zx296718.dtsi cvs rdiff -u -r1.1.1.3 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/zte/zx296718-evb.dts cvs rdiff -u -r1.1.1.1 -r0 \ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/zte/zx296718-pcbox.dts cvs rdiff -u -r1.1.1.1 -r0 \ src/sys/external/gpl2/dts/dist/include/dt-bindings/clk/ti-dra7-atl.h cvs rdiff -u -r1.1 -r1.2 \ src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/sun50i-h6-r-ccu.h cvs rdiff -u -r1.1.1.2 -r0 \ src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/zx296702-clock.h cvs rdiff -u -r1.1.1.3 -r0 \ src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/zx296718-clock.h cvs rdiff -u -r1.9 -r1.10 \ src/sys/external/gpl2/dts/dist/include/dt-bindings/input/linux-event-codes.h cvs rdiff -u -r1.1 -r1.2 \ src/sys/external/gpl2/dts/dist/include/dt-bindings/reset/sun50i-h6-r-ccu.h cvs rdiff -u -r1.1.1.2 -r0 \ src/sys/external/gpl2/dts/dist/include/dt-bindings/soc/zte,pm_domains.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/bcm2835-common.dtsi diff -u src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/bcm2835-common.dtsi:1.3 src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/bcm2835-common.dtsi:1.4 --- src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/bcm2835-common.dtsi:1.3 Fri Jan 3 15:40:38 2020 +++ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/bcm2835-common.dtsi Sun Nov 7 16:57:37 2021 @@ -70,6 +70,12 @@ system-power-controller; }; + rng@7e104000 { + compatible = "brcm,bcm2835-rng"; + reg = <0x7e104000 0x10>; + interrupts = <2 29>; + }; + pixelvalve@7e206000 { compatible = "brcm,bcm2835-pixelvalve0"; reg = <0x7e206000 0x100>; @@ -102,6 +108,14 @@ status = "okay"; }; + vec: vec@7e806000 { + compatible = "brcm,bcm2835-vec"; + reg = <0x7e806000 0x1000>; + clocks = <&clocks BCM2835_CLOCK_VEC>; + interrupts = <2 27>; + status = "disabled"; + }; + pixelvalve@7e807000 { compatible = "brcm,bcm2835-pixelvalve2"; reg = <0x7e807000 0x100>; Index: src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts diff -u src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts:1.2 src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts:1.3 --- src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts:1.2 Sat Feb 22 09:54:27 2020 +++ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts Sun Nov 7 16:57:37 2021 @@ -23,8 +23,8 @@ }; leds { - act { - gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; + led-act { + gpios = <&gpio 47 GPIO_ACTIVE_LOW>; }; }; Index: src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/bcm2835-rpi.dtsi diff -u src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/bcm2835-rpi.dtsi:1.7 src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/bcm2835-rpi.dtsi:1.8 --- src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/bcm2835-rpi.dtsi:1.7 Fri Jan 3 15:04:33 2020 +++ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/bcm2835-rpi.dtsi Sun Nov 7 16:57:37 2021 @@ -4,7 +4,7 @@ leds { compatible = "gpio-leds"; - act { + led-act { label = "ACT"; default-state = "keep"; linux,default-trigger = "heartbeat"; @@ -13,8 +13,12 @@ soc { firmware: firmware { - compatible = "raspberrypi,bcm2835-firmware", "simple-bus"; + compatible = "raspberrypi,bcm2835-firmware", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + mboxes = <&mailbox>; + dma-ranges; }; power: power { Index: src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/bcm283x.dtsi diff -u src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/bcm283x.dtsi:1.9 src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/bcm283x.dtsi:1.10 --- src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/bcm283x.dtsi:1.9 Fri Jan 3 15:04:33 2020 +++ src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/bcm283x.dtsi Sun Nov 7 16:57:37 2021 @@ -30,6 +30,19 @@ stdout-path = "serial0:115200n8"; }; + rmem: reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + size = <0x4000000>; /* 64MB */ + reusable; + linux,cma-default; + }; + }; + thermal-zones { cpu_thermal: cpu-thermal { polling-delay-passive = <0>; @@ -84,12 +97,6 @@ <&dsi1 0>, <&dsi1 1>, <&dsi1 2>; }; - rng@7e104000 { - compatible = "brcm,bcm2835-rng"; - reg = <0x7e104000 0x10>; - interrupts = <2 29>; - }; - mailbox: mailbox@7e00b880 { compatible = "brcm,bcm2835-mbox"; reg = <0x7e00b880 0x40>; @@ -365,6 +372,7 @@ "dsi0_ddr2", "dsi0_ddr"; + status = "disabled"; }; aux: aux@7e215000 { @@ -412,7 +420,7 @@ status = "disabled"; }; - sdhci: sdhci@7e300000 { + sdhci: mmc@7e300000 { compatible = "brcm,bcm2835-sdhci"; reg = <0x7e300000 0x100>; interrupts = <2 30>; @@ -457,14 +465,6 @@ status = "disabled"; }; - vec: vec@7e806000 { - compatible = "brcm,bcm2835-vec"; - reg = <0x7e806000 0x1000>; - clocks = <&clocks BCM2835_CLOCK_VEC>; - interrupts = <2 27>; - status = "disabled"; - }; - usb: usb@7e980000 { compatible = "brcm,bcm2835-usb"; reg = <0x7e980000 0x10000>; Index: src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts diff -u src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts:1.3 src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts:1.4 --- src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts:1.3 Fri Jan 3 15:04:33 2020 +++ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts Sun Nov 7 16:57:38 2021 @@ -1,45 +1,6 @@ -/* - * Copyright (C) 2017 Antony Antony <ant...@phenome.org> - * Copyright (C) 2016 ARM Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2017 Antony Antony <ant...@phenome.org> +// Copyright (C) 2016 ARM Ltd. /dts-v1/; #include "sun50i-h5.dtsi" @@ -64,15 +25,15 @@ leds { compatible = "gpio-leds"; - pwr { + led-0 { label = "nanopi:green:pwr"; gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; default-state = "on"; }; - status { - label = "nanopi:blue:status"; - gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; + led-1 { + label = "nanopi:red:status"; + gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>; }; }; @@ -135,7 +96,7 @@ pinctrl-0 = <&emac_rgmii_pins>; phy-supply = <®_gmac_3v3>; phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; status = "okay"; }; Index: src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts diff -u src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts:1.7 src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts:1.8 --- src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts:1.7 Fri Jan 3 16:29:42 2020 +++ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts Sun Nov 7 16:57:38 2021 @@ -1,31 +1,38 @@ -/* - * Copyright (c) 2017 Icenowy Zheng <icen...@aosc.io> - * - * SPDX-License-Identifier: (GPL-2.0+ or MIT) - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2017 Icenowy Zheng <icen...@aosc.io> /dts-v1/; #include "sun50i-h6.dtsi" +#include "sun50i-h6-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> / { - model = "Pine H64"; + model = "Pine H64 model A"; compatible = "pine64,pine-h64", "allwinner,sun50i-h6"; aliases { ethernet0 = &emac; serial0 = &uart0; + spi0 = &spi0; }; chosen { stdout-path = "serial0:115200n8"; }; - connector { + ext_osc32k: ext_osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "ext_osc32k"; + }; + + hdmi_connector: connector { compatible = "hdmi-connector"; type = "a"; + ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ port { hdmi_con_in: endpoint { @@ -37,22 +44,32 @@ leds { compatible = "gpio-leds"; - heartbeat { + led-0 { label = "pine-h64:green:heartbeat"; gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ }; - link { + led-1 { label = "pine-h64:white:link"; gpios = <&r_pio 0 3 GPIO_ACTIVE_HIGH>; /* PL3 */ }; - status { + led-2 { label = "pine-h64:blue:status"; gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ }; }; + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc-gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usb_vbus: vbus { compatible = "regulator-fixed"; regulator-name = "usb-vbus"; @@ -64,28 +81,33 @@ }; }; +&cpu0 { + cpu-supply = <®_dcdca>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + &emac { pinctrl-names = "default"; pinctrl-0 = <&ext_rgmii_pins>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <&ext_rgmii_phy>; - phy-supply = <®_aldo2>; + phy-supply = <®_gmac_3v3>; allwinner,rx-delay-ps = <200>; allwinner,tx-delay-ps = <200>; status = "okay"; }; -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&de { - status = "okay"; -}; - &gpu { mali-supply = <®_dcdcc>; status = "okay"; @@ -101,12 +123,11 @@ }; }; -&ehci0 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; }; &mmc0 { @@ -121,6 +142,7 @@ vqmmc-supply = <®_bldo2>; non-removable; cap-mmc-hw-reset; + mmc-hs200-1_8v; bus-width = <8>; status = "okay"; }; @@ -146,7 +168,7 @@ compatible = "x-powers,axp805", "x-powers,axp806"; reg = <0x36>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; x-powers,self-working-mode; @@ -222,7 +244,8 @@ reg_dcdca: dcdca { regulator-always-on; regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; + regulator-max-microvolt = <1160000>; + regulator-ramp-delay = <2500>; regulator-name = "vdd-cpu"; }; @@ -230,6 +253,7 @@ regulator-enable-ramp-delay = <32000>; regulator-min-microvolt = <810000>; regulator-max-microvolt = <1080000>; + regulator-ramp-delay = <2500>; regulator-name = "vdd-gpu"; }; @@ -257,7 +281,7 @@ compatible = "nxp,pcf8563"; reg = <0x51>; interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>; #clock-cells = <0>; }; }; @@ -270,6 +294,28 @@ vcc-pm-supply = <®_aldo1>; }; +&rtc { + clocks = <&ext_osc32k>; +}; + +/* + * The CS pin is shared with the MMC2 CMD pin, so we cannot have the SPI + * flash and eMMC at the same time, as one of them would fail probing. + * Disable SPI0 in here, to prefer the more useful eMMC. U-Boot can + * fix this up in no eMMC is connected. + */ +&spi0 { + pinctrl-0 = <&spi0_pins>, <&spi0_cs_pin>; + pinctrl-names = "default"; + status = "disabled"; + + flash@0 { + compatible = "winbond,w25q128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <4000000>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_ph_pins>; Index: src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi diff -u src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi:1.7 src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi:1.8 --- src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi:1.7 Fri Jan 3 15:04:33 2020 +++ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi Sun Nov 7 16:57:38 2021 @@ -1,8 +1,5 @@ -/* - * Copyright (C) 2017 Icenowy Zheng <icen...@aosc.io> - * - * SPDX-License-Identifier: (GPL-2.0+ or MIT) - */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2017 Icenowy Zheng <icen...@aosc.io> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/sun50i-h6-ccu.h> @@ -12,6 +9,7 @@ #include <dt-bindings/reset/sun50i-h6-ccu.h> #include <dt-bindings/reset/sun50i-h6-r-ccu.h> #include <dt-bindings/reset/sun8i-de2.h> +#include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&gic>; @@ -44,10 +42,8 @@ device_type = "cpu"; reg = <0>; enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - operating-points-v2 = <&cpu0_opp_table>; + clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; }; @@ -56,7 +52,9 @@ device_type = "cpu"; reg = <1>; enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; + clocks = <&ccu CLK_CPUX>; + clock-latency-ns = <244144>; /* 8 32k periods */ + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -64,7 +62,9 @@ device_type = "cpu"; reg = <2>; enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; + clocks = <&ccu CLK_CPUX>; + clock-latency-ns = <244144>; /* 8 32k periods */ + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -72,7 +72,9 @@ device_type = "cpu"; reg = <3>; enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; + clocks = <&ccu CLK_CPUX>; + clock-latency-ns = <244144>; /* 8 32k periods */ + #cooling-cells = <2>; }; }; @@ -89,11 +91,13 @@ clock-output-names = "osc24M"; }; - ext_osc32k: ext_osc32k_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "ext_osc32k"; + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; psci { @@ -103,6 +107,7 @@ timer { compatible = "arm,armv8-timer"; + arm,no-tick-in-suspend; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 14 @@ -148,6 +153,7 @@ clock-names = "bus", "mod"; resets = <&display_clocks RST_MIXER0>; + iommus = <&iommu 0>; ports { #address-cells = <1>; @@ -173,6 +179,7 @@ resets = <&ccu RST_BUS_VE>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; allwinner,sram = <&ve_sram 1>; + iommus = <&iommu 3>; }; gpu: gpu@1800000 { @@ -256,9 +263,38 @@ #dma-cells = <1>; }; + msgbox: mailbox@3003000 { + compatible = "allwinner,sun50i-h6-msgbox", + "allwinner,sun6i-a31-msgbox"; + reg = <0x03003000 0x1000>; + clocks = <&ccu CLK_BUS_MSGBOX>; + resets = <&ccu RST_BUS_MSGBOX>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + }; + sid: efuse@3006000 { compatible = "allwinner,sun50i-h6-sid"; reg = <0x03006000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + ths_calibration: thermal-sensor-calibration@14 { + reg = <0x14 0x8>; + }; + + cpu_speed_grade: cpu-speed-grade@1c { + reg = <0x1c 0x4>; + }; + }; + + timer@3009000 { + compatible = "allwinner,sun50i-h6-timer", + "allwinner,sun8i-a23-timer"; + reg = <0x03009000 0xa0>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24M>; }; watchdog: watchdog@30090a0 { @@ -271,9 +307,20 @@ status = "disabled"; }; + pwm: pwm@300a000 { + compatible = "allwinner,sun50i-h6-pwm"; + reg = <0x0300a000 0x400>; + clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; + clock-names = "mod", "bus"; + resets = <&ccu RST_BUS_PWM>; + #pwm-cells = <3>; + status = "disabled"; + }; + pio: pinctrl@300b000 { compatible = "allwinner,sun50i-h6-pinctrl"; reg = <0x0300b000 0x400>; + interrupt-parent = <&r_intc>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, @@ -339,6 +386,31 @@ bias-pull-up; }; + /omit-if-no-ref/ + spi0_pins: spi0-pins { + pins = "PC0", "PC2", "PC3"; + function = "spi0"; + }; + + /* pin shared with MMC2-CMD (eMMC) */ + /omit-if-no-ref/ + spi0_cs_pin: spi0-cs-pin { + pins = "PC5"; + function = "spi0"; + }; + + /omit-if-no-ref/ + spi1_pins: spi1-pins { + pins = "PH4", "PH5", "PH6"; + function = "spi1"; + }; + + /omit-if-no-ref/ + spi1_cs_pin: spi1-cs-pin { + pins = "PH3"; + function = "spi1"; + }; + spdif_tx_pin: spdif-tx-pin { pins = "PH7"; function = "spdif"; @@ -371,6 +443,15 @@ #interrupt-cells = <3>; }; + iommu: iommu@30f0000 { + compatible = "allwinner,sun50i-h6-iommu"; + reg = <0x030f0000 0x10000>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_IOMMU>; + resets = <&ccu RST_BUS_IOMMU>; + #iommu-cells = <1>; + }; + mmc0: mmc@4020000 { compatible = "allwinner,sun50i-h6-mmc", "allwinner,sun50i-a64-mmc"; @@ -382,6 +463,7 @@ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; + max-frequency = <150000000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -398,6 +480,7 @@ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; + max-frequency = <150000000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -414,6 +497,7 @@ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; + max-frequency = <150000000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -505,6 +589,36 @@ #size-cells = <0>; }; + spi0: spi@5010000 { + compatible = "allwinner,sun50i-h6-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x05010000 0x1000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + dmas = <&dma 22>, <&dma 22>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@5011000 { + compatible = "allwinner,sun50i-h6-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x05011000 0x1000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + emac: ethernet@5020000 { compatible = "allwinner,sun50i-h6-emac", "allwinner,sun50i-a64-emac"; @@ -525,6 +639,19 @@ }; }; + i2s1: i2s@5091000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun50i-h6-i2s"; + reg = <0x05091000 0x1000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; + clock-names = "apb", "mod"; + dmas = <&dma 4>, <&dma 4>; + resets = <&ccu RST_BUS_I2S1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + spdif: spdif@5093000 { #sound-dai-cells = <0>; compatible = "allwinner,sun50i-h6-spdif"; @@ -583,6 +710,8 @@ <&ccu CLK_USB_OHCI0>; resets = <&ccu RST_BUS_OHCI0>, <&ccu RST_BUS_EHCI0>; + phys = <&usb2phy 0>; + phy-names = "usb"; status = "disabled"; }; @@ -593,10 +722,12 @@ clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>; resets = <&ccu RST_BUS_OHCI0>; + phys = <&usb2phy 0>; + phy-names = "usb"; status = "disabled"; }; - dwc3: dwc3@5200000 { + dwc3: usb@5200000 { compatible = "snps,dwc3"; reg = <0x05200000 0x10000>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; @@ -798,10 +929,10 @@ rtc: rtc@7000000 { compatible = "allwinner,sun50i-h6-rtc"; reg = <0x07000000 0x400>; + interrupt-parent = <&r_intc>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; clock-output-names = "osc32k", "osc32k-out", "iosc"; - clocks = <&ext_osc32k>; #clock-cells = <1>; }; @@ -824,10 +955,9 @@ }; r_intc: interrupt-controller@7021000 { - compatible = "allwinner,sun50i-h6-r-intc", - "allwinner,sun6i-a31-r-intc"; + compatible = "allwinner,sun50i-h6-r-intc"; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <3>; reg = <0x07021000 0x400>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; }; @@ -835,6 +965,7 @@ r_pio: pinctrl@7022000 { compatible = "allwinner,sun50i-h6-r-pinctrl"; reg = <0x07022000 0x400>; + interrupt-parent = <&r_intc>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; @@ -853,6 +984,11 @@ pins = "PL9"; function = "s_cir_rx"; }; + + r_rsb_pins: r-rsb-pins { + pins = "PL0", "PL1"; + function = "s_rsb"; + }; }; r_ir: ir@7040000 { @@ -882,5 +1018,69 @@ #address-cells = <1>; #size-cells = <0>; }; + + r_rsb: rsb@7083000 { + compatible = "allwinner,sun8i-a23-rsb"; + reg = <0x07083000 0x400>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_R_APB2_RSB>; + clock-frequency = <3000000>; + resets = <&r_ccu RST_R_APB2_RSB>; + pinctrl-names = "default"; + pinctrl-0 = <&r_rsb_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + ths: thermal-sensor@5070400 { + compatible = "allwinner,sun50i-h6-ths"; + reg = <0x05070400 0x100>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_THS>; + clock-names = "bus"; + resets = <&ccu RST_BUS_THS>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; + }; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; + + trips { + cpu_alert: cpu-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 1>; + }; }; }; Index: src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/Makefile diff -u src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/Makefile:1.3 src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/Makefile:1.4 --- src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/Makefile:1.3 Sat Jan 2 08:38:55 2021 +++ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/Makefile Sun Nov 7 16:57:38 2021 @@ -3,10 +3,15 @@ dtb-$(CONFIG_ARCH_MESON) += meson-axg-s4 dtb-$(CONFIG_ARCH_MESON) += meson-g12a-sei510.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-x96-max.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gsking-x.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-khadas-vim3.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2-plus.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-ugoos-am6.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-kii-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb @@ -21,20 +26,31 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s8 dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-hwacom-amazetv.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-khadas-vim.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc-v2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-mecool-kii-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-phicomm-n1.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-sml5442tw.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-p281.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-tx3-mini.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-libretech-pc.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxm-mecool-kiii-pro.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxm-minix-neo-u9h.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-libretech-pc.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxm-wetek-core2.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-sm1-bananapi-m5.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-c4.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-hc4.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb Index: src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/meson-gx.dtsi diff -u src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/meson-gx.dtsi:1.4 src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/meson-gx.dtsi:1.5 --- src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/meson-gx.dtsi:1.4 Fri Jan 3 15:04:33 2020 +++ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/meson-gx.dtsi Sun Nov 7 16:57:38 2021 @@ -12,12 +12,20 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/meson-gxbb-power.h> +#include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; + aliases { + mmc0 = &sd_emmc_b; /* SD card */ + mmc1 = &sd_emmc_c; /* eMMC */ + mmc2 = &sd_emmc_a; /* SDIO */ + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -59,7 +67,7 @@ compatible = "amlogic,simple-framebuffer", "simple-framebuffer"; amlogic,pipeline = "vpu-cvbs"; - power-domains = <&pwrc_vpu>; + power-domains = <&pwrc PWRC_GXBB_VPU_ID>; status = "disabled"; }; @@ -67,7 +75,7 @@ compatible = "amlogic,simple-framebuffer", "simple-framebuffer"; amlogic,pipeline = "vpu-hdmi"; - power-domains = <&pwrc_vpu>; + power-domains = <&pwrc PWRC_GXBB_VPU_ID>; status = "disabled"; }; }; @@ -83,6 +91,7 @@ enable-method = "psci"; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -92,6 +101,7 @@ enable-method = "psci"; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -101,6 +111,7 @@ enable-method = "psci"; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -110,6 +121,7 @@ enable-method = "psci"; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; + #cooling-cells = <2>; }; l2: l2-cache0 { @@ -117,6 +129,53 @@ }; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + + thermal-sensors = <&scpi_sensors 0>; + + trips { + cpu_passive: cpu-passive { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + cpu_hot: cpu-hot { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "hot"; + }; + + cpu_critical: cpu-critical { + temperature = <110000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cpu_cooling_maps: cooling-maps { + map0 { + trip = <&cpu_passive>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&cpu_hot>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + arm-pmu { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, @@ -226,11 +285,23 @@ #reset-cells = <1>; }; + aiu: audio-controller@5400 { + compatible = "amlogic,aiu"; + #sound-dai-cells = <2>; + sound-name-prefix = "AIU"; + reg = <0x0 0x5400 0x0 0x2ac>; + interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "i2s", "spdif"; + status = "disabled"; + }; + uart_A: serial@84c0 { compatible = "amlogic,meson-gx-uart"; reg = <0x0 0x84c0 0x0 0x18>; interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; status = "disabled"; + fifo-size = <128>; }; uart_B: serial@84dc { @@ -346,20 +417,20 @@ }; sram: sram@c8000000 { - compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram"; + compatible = "mmio-sram"; reg = <0x0 0xc8000000 0x0 0x14000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x0 0xc8000000 0x14000>; - cpu_scp_lpri: scp-shmem@0 { - compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; + cpu_scp_lpri: scp-sram@0 { + compatible = "amlogic,meson-gxbb-scp-shmem"; reg = <0x13000 0x400>; }; - cpu_scp_hpri: scp-shmem@200 { - compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; + cpu_scp_hpri: scp-sram@200 { + compatible = "amlogic,meson-gxbb-scp-shmem"; reg = <0x13400 0x400>; }; }; @@ -375,12 +446,6 @@ compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon"; reg = <0x0 0x0 0x0 0x100>; - pwrc_vpu: power-controller-vpu { - compatible = "amlogic,meson-gx-pwrc-vpu"; - #power-domain-cells = <0>; - amlogic,hhi-sysctrl = <&sysctrl>; - }; - clkc_AO: clock-controller { compatible = "amlogic,meson-gx-aoclkc"; #clock-cells = <1>; @@ -489,6 +554,12 @@ sysctrl: system-controller@0 { compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"; reg = <0 0 0 0x400>; + + pwrc: power-controller { + compatible = "amlogic,meson-gxbb-pwrc"; + #power-domain-cells = <1>; + amlogic,ao-sysctrl = <&sysctrl_AO>; + }; }; mailbox: mailbox@404 { @@ -511,6 +582,7 @@ interrupt-names = "macirq"; rx-fifo-depth = <4096>; tx-fifo-depth = <2048>; + power-domains = <&pwrc PWRC_GXBB_ETHERNET_MEM_ID>; status = "disabled"; }; @@ -574,6 +646,8 @@ interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; #address-cells = <1>; #size-cells = <0>; + #sound-dai-cells = <0>; + sound-name-prefix = "HDMITX"; status = "disabled"; /* VPU VENC Input */ Index: src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi diff -u src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi:1.4 src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi:1.5 --- src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi:1.4 Fri Jan 3 15:04:33 2020 +++ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi Sun Nov 7 16:57:38 2021 @@ -4,6 +4,7 @@ */ #include "meson-gx.dtsi" +#include "meson-gx-mali450.dtsi" #include <dt-bindings/gpio/meson-gxbb-gpio.h> #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> #include <dt-bindings/clock/gxbb-clkc.h> @@ -60,6 +61,29 @@ }; }; +&aiu { + compatible = "amlogic,aiu-gxbb", "amlogic,aiu"; + clocks = <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_CTS_AMCLK>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>, + <&clkc CLKID_CTS_MCLK_I958>, + <&clkc CLKID_CTS_I958>; + clock-names = "pclk", + "i2s_pclk", + "i2s_aoclk", + "i2s_mclk", + "i2s_mixer", + "spdif_pclk", + "spdif_aoclk", + "spdif_mclk", + "spdif_mclk_sel"; + resets = <&reset RESET_AIU>; +}; + &aobus { pinctrl_aobus: pinctrl@14 { compatible = "amlogic,meson-gxbb-aobus-pinctrl"; @@ -241,46 +265,6 @@ }; }; -&apb { - mali: gpu@c0000 { - compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; - reg = <0x0 0xc0000 0x0 0x40000>; - interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gp", "gpmmu", "pp", "pmu", - "pp0", "ppmmu0", "pp1", "ppmmu1", - "pp2", "ppmmu2"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; - clock-names = "bus", "core"; - - /* - * Mali clocking is provided by two identical clock paths - * MALI_0 and MALI_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - */ - assigned-clocks = <&clkc CLKID_GP0_PLL>, - <&clkc CLKID_MALI_0_SEL>, - <&clkc CLKID_MALI_0>, - <&clkc CLKID_MALI>; /* Glitch free mux */ - assigned-clock-parents = <0>, /* Do Nothing */ - <&clkc CLKID_GP0_PLL>, - <0>, /* Do Nothing */ - <&clkc CLKID_MALI_0>; - assigned-clock-rates = <744000000>, - <0>, /* Do Nothing */ - <744000000>, - <0>; /* Do Nothing */ - }; -}; - &cbus { spifc: spi@8c80 { compatible = "amlogic,meson-gxbb-spifc"; @@ -310,8 +294,9 @@ ðmac { clocks = <&clkc CLKID_ETH>, <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; + <&clkc CLKID_MPLL2>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; }; &gpio_intc { @@ -362,6 +347,16 @@ clocks = <&clkc CLKID_I2C>; }; +&mali { + compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; + + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; + clock-names = "bus", "core"; + + assigned-clocks = <&clkc CLKID_GP0_PLL>; + assigned-clock-rates = <744000000>; +}; + &periphs { pinctrl_periphs: pinctrl@4b0 { compatible = "amlogic,meson-gxbb-periphs-pinctrl"; @@ -724,7 +719,7 @@ }; }; -&pwrc_vpu { +&pwrc { resets = <&reset RESET_VIU>, <&reset RESET_VENC>, <&reset RESET_VCBUS>, @@ -737,6 +732,9 @@ <&reset RESET_VDI6>, <&reset RESET_VENCL>, <&reset RESET_VID_LOCK>; + reset-names = "viu", "venc", "vcbus", "bt656", + "dvin", "rdma", "venci", "vencp", + "vdac", "vdi6", "vencl", "vid_lock"; clocks = <&clkc CLKID_VPU>, <&clkc CLKID_VAPB>; clock-names = "vpu", "vapb"; @@ -843,7 +841,7 @@ &vpu { compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu"; - power-domains = <&pwrc_vpu>; + power-domains = <&pwrc PWRC_GXBB_VPU_ID>; }; &vdec { Index: src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi diff -u src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi:1.4 src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi:1.5 --- src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi:1.4 Fri Jan 3 15:04:33 2020 +++ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi Sun Nov 7 16:57:38 2021 @@ -14,29 +14,57 @@ compatible = "amlogic,meson-gxl"; soc { - usb0: usb@c9000000 { - status = "disabled"; - compatible = "amlogic,meson-gxl-dwc3"; + usb: usb@d0078080 { + compatible = "amlogic,meson-gxl-usb-ctrl"; + reg = <0x0 0xd0078080 0x0 0x20>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <2>; #size-cells = <2>; ranges; - clocks = <&clkc CLKID_USB>; - clock-names = "usb_general"; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>; + clock-names = "usb_ctrl", "ddr"; resets = <&reset RESET_USB_OTG>; - reset-names = "usb_otg"; - dwc3: dwc3@c9000000 { + dr_mode = "otg"; + + phys = <&usb2_phy0>, <&usb2_phy1>; + phy-names = "usb2-phy0", "usb2-phy1"; + + dwc2: usb@c9100000 { + compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; + reg = <0x0 0xc9100000 0x0 0x40000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc CLKID_USB1>; + clock-names = "otg"; + phys = <&usb2_phy1>; + dr_mode = "peripheral"; + g-rx-fifo-size = <192>; + g-np-tx-fifo-size = <128>; + g-tx-fifo-size = <128 128 16 16 16>; + }; + + dwc3: usb@c9000000 { compatible = "snps,dwc3"; reg = <0x0 0xc9000000 0x0 0x100000>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; - phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>; }; }; + acodec: audio-controller@c8832000 { + compatible = "amlogic,t9015"; + reg = <0x0 0xc8832000 0x0 0x14>; + #sound-dai-cells = <0>; + sound-name-prefix = "ACODEC"; + clocks = <&clkc CLKID_ACODEC>; + clock-names = "pclk"; + resets = <&reset RESET_ACODEC>; + status = "disabled"; + }; + crypto: crypto@c883e000 { compatible = "amlogic,gxl-crypto"; reg = <0x0 0xc883e000 0x0 0x36>; @@ -49,6 +77,29 @@ }; }; +&aiu { + compatible = "amlogic,aiu-gxl", "amlogic,aiu"; + clocks = <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_CTS_AMCLK>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>, + <&clkc CLKID_CTS_MCLK_I958>, + <&clkc CLKID_CTS_I958>; + clock-names = "pclk", + "i2s_pclk", + "i2s_aoclk", + "i2s_mclk", + "i2s_mixer", + "spdif_pclk", + "spdif_aoclk", + "spdif_mclk", + "spdif_mclk_sel"; + resets = <&reset RESET_AIU>; +}; + &apb { usb2_phy0: phy@78000 { compatible = "amlogic,meson-gxl-usb2-phy"; @@ -71,18 +122,6 @@ reset-names = "phy"; status = "okay"; }; - - usb3_phy: phy@78080 { - compatible = "amlogic,meson-gxl-usb3-phy"; - #phy-cells = <0>; - reg = <0x0 0x78080 0x0 0x20>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>; - clock-names = "phy", "peripheral"; - resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>; - reset-names = "phy", "peripheral"; - status = "okay"; - }; }; &efuse { @@ -92,8 +131,9 @@ ðmac { clocks = <&clkc CLKID_ETH>, <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; + <&clkc CLKID_MPLL2>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; mdio0: mdio { #address-cells = <1>; @@ -298,6 +338,11 @@ }; }; +&hwrng { + clocks = <&clkc CLKID_RNG0>; + clock-names = "core"; +}; + &i2c_A { clocks = <&clkc CLKID_I2C>; }; @@ -533,6 +578,15 @@ }; }; + i2c_c_dv18_pins: i2c_c_dv18 { + mux { + groups = "i2c_sck_c_dv19", + "i2c_sda_c_dv18"; + function = "i2c_c"; + bias-disable; + }; + }; + eth_pins: eth_c { mux { groups = "eth_mdio", @@ -734,7 +788,7 @@ }; }; -&pwrc_vpu { +&pwrc { resets = <&reset RESET_VIU>, <&reset RESET_VENC>, <&reset RESET_VCBUS>, @@ -747,6 +801,9 @@ <&reset RESET_VDI6>, <&reset RESET_VENCL>, <&reset RESET_VID_LOCK>; + reset-names = "viu", "venc", "vcbus", "bt656", + "dvin", "rdma", "venci", "vencp", + "vdac", "vdi6", "vencl", "vid_lock"; clocks = <&clkc CLKID_VPU>, <&clkc CLKID_VAPB>; clock-names = "vpu", "vapb"; @@ -853,7 +910,7 @@ &vpu { compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu"; - power-domains = <&pwrc_vpu>; + power-domains = <&pwrc PWRC_GXBB_VPU_ID>; }; &vdec { Index: src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi diff -u src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi:1.6 src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi:1.7 --- src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi:1.6 Fri Jan 3 15:04:33 2020 +++ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi Sun Nov 7 16:57:38 2021 @@ -17,21 +17,155 @@ * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT * CHANGES TO vexpress-v2m.dtsi! */ +#include <dt-bindings/interrupt-controller/arm-gic.h> / { - smb@8000000 { - motherboard { - model = "V2M-P1"; + v2m_fixed_3v3: fixed-regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + leds { + compatible = "gpio-leds"; + + led-1 { + label = "v2m:green:user1"; + gpios = <&v2m_led_gpios 0 0>; + linux,default-trigger = "heartbeat"; + }; + + led-2 { + label = "v2m:green:user2"; + gpios = <&v2m_led_gpios 1 0>; + linux,default-trigger = "disk-activity"; + }; + + led-3 { + label = "v2m:green:user3"; + gpios = <&v2m_led_gpios 2 0>; + linux,default-trigger = "cpu0"; + }; + + led-4 { + label = "v2m:green:user4"; + gpios = <&v2m_led_gpios 3 0>; + linux,default-trigger = "cpu1"; + }; + + led-5 { + label = "v2m:green:user5"; + gpios = <&v2m_led_gpios 4 0>; + linux,default-trigger = "cpu2"; + }; + + led-6 { + label = "v2m:green:user6"; + gpios = <&v2m_led_gpios 5 0>; + linux,default-trigger = "cpu3"; + }; + + led-7 { + label = "v2m:green:user7"; + gpios = <&v2m_led_gpios 6 0>; + linux,default-trigger = "cpu4"; + }; + + led-8 { + label = "v2m:green:user8"; + gpios = <&v2m_led_gpios 7 0>; + linux,default-trigger = "cpu5"; + }; + }; + + bus@8000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 63>; + interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + + motherboard-bus@8000000 { arm,hbi = <0x190>; arm,vexpress,site = <0>; - arm,v2m-memory-map = "rs1"; compatible = "arm,vexpress,v2m-p1", "simple-bus"; #address-cells = <2>; /* SMB chipselect number and offset */ #size-cells = <1>; - #interrupt-cells = <1>; - ranges; + ranges = <0 0 0x08000000 0x04000000>, + <1 0 0x14000000 0x04000000>, + <2 0 0x18000000 0x04000000>, + <3 0 0x1c000000 0x04000000>, + <4 0 0x0c000000 0x04000000>, + <5 0 0x10000000 0x04000000>; - nor_flash: flash@0,00000000 { + nor_flash: flash@0 { compatible = "arm,vexpress-flash", "cfi-flash"; reg = <0 0x00000000 0x04000000>, <4 0x00000000 0x04000000>; @@ -41,13 +175,13 @@ }; }; - psram@1,00000000 { + psram@100000000 { compatible = "arm,vexpress-psram", "mtd-ram"; reg = <1 0x00000000 0x02000000>; bank-width = <4>; }; - ethernet@2,02000000 { + ethernet@202000000 { compatible = "smsc,lan9118", "smsc,lan9115"; reg = <2 0x02000000 0x10000>; interrupts = <15>; @@ -59,14 +193,14 @@ vddvario-supply = <&v2m_fixed_3v3>; }; - usb@2,03000000 { + usb@203000000 { compatible = "nxp,usb-isp1761"; reg = <2 0x03000000 0x20000>; interrupts = <16>; - port1-otg; + dr_mode = "peripheral"; }; - iofpga@3,00000000 { + iofpga-bus@300000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -134,7 +268,7 @@ clock-names = "apb_pclk"; }; - mmci@50000 { + mmc@50000 { compatible = "arm,pl180", "arm,primecell"; reg = <0x050000 0x1000>; interrupts = <9>, <10>; @@ -162,7 +296,7 @@ clock-names = "KMIREFCLK", "apb_pclk"; }; - v2m_serial0: uart@90000 { + v2m_serial0: serial@90000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x090000 0x1000>; interrupts = <5>; @@ -170,7 +304,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial1: uart@a0000 { + v2m_serial1: serial@a0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0a0000 0x1000>; interrupts = <6>; @@ -178,7 +312,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial2: uart@b0000 { + v2m_serial2: serial@b0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0b0000 0x1000>; interrupts = <7>; @@ -186,7 +320,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial3: uart@c0000 { + v2m_serial3: serial@c0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0c0000 0x1000>; interrupts = <8>; @@ -194,12 +328,12 @@ clock-names = "uartclk", "apb_pclk"; }; - wdt@f0000 { + watchdog@f0000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0f0000 0x1000>; interrupts = <0>; clocks = <&v2m_refclk32khz>, <&smbclk>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; }; v2m_timer01: timer@110000 { @@ -281,159 +415,78 @@ }; }; }; - }; - - v2m_fixed_3v3: fixed-regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - - leds { - compatible = "gpio-leds"; - - user1 { - label = "v2m:green:user1"; - gpios = <&v2m_led_gpios 0 0>; - linux,default-trigger = "heartbeat"; - }; - - user2 { - label = "v2m:green:user2"; - gpios = <&v2m_led_gpios 1 0>; - linux,default-trigger = "mmc0"; - }; - - user3 { - label = "v2m:green:user3"; - gpios = <&v2m_led_gpios 2 0>; - linux,default-trigger = "cpu0"; - }; - - user4 { - label = "v2m:green:user4"; - gpios = <&v2m_led_gpios 3 0>; - linux,default-trigger = "cpu1"; - }; - - user5 { - label = "v2m:green:user5"; - gpios = <&v2m_led_gpios 4 0>; - linux,default-trigger = "cpu2"; - }; - user6 { - label = "v2m:green:user6"; - gpios = <&v2m_led_gpios 5 0>; - linux,default-trigger = "cpu3"; - }; - - user7 { - label = "v2m:green:user7"; - gpios = <&v2m_led_gpios 6 0>; - linux,default-trigger = "cpu4"; - }; - - user8 { - label = "v2m:green:user8"; - gpios = <&v2m_led_gpios 7 0>; - linux,default-trigger = "cpu5"; - }; - }; - - mcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* MCC static memory clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <25000000 60000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk0"; - }; + mcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + oscclk0 { + /* MCC static memory clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <25000000 60000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk0"; + }; - v2m_oscclk1: oscclk1 { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 65000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; - }; + v2m_oscclk1: oscclk1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 65000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; - v2m_oscclk2: oscclk2 { - /* IO FPGA peripheral clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <24000000 24000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk2"; - }; + v2m_oscclk2: oscclk2 { + /* IO FPGA peripheral clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <24000000 24000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk2"; + }; - volt-vio { - /* Logic level voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VIO"; - regulator-always-on; - label = "VIO"; - }; + volt-vio { + /* Logic level voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 0>; + regulator-name = "VIO"; + regulator-always-on; + label = "VIO"; + }; - temp-mcc { - /* MCC internal operating temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "MCC"; - }; + temp-mcc { + /* MCC internal operating temperature */ + compatible = "arm,vexpress-temp"; + arm,vexpress-sysreg,func = <4 0>; + label = "MCC"; + }; - reset { - compatible = "arm,vexpress-reset"; - arm,vexpress-sysreg,func = <5 0>; - }; + reset { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; + }; - muxfpga { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; + muxfpga { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; - shutdown { - compatible = "arm,vexpress-shutdown"; - arm,vexpress-sysreg,func = <8 0>; - }; + shutdown { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; - reboot { - compatible = "arm,vexpress-reboot"; - arm,vexpress-sysreg,func = <9 0>; - }; + reboot { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; - dvimode { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; + dvimode { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; }; }; }; Index: src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts diff -u src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts:1.4 src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts:1.5 --- src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts:1.4 Fri Jan 3 15:04:34 2020 +++ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts Sun Nov 7 16:57:39 2021 @@ -10,6 +10,11 @@ model = "Pine64 Rock64"; compatible = "pine64,rock64", "rockchip,rk3328"; + aliases { + mmc0 = &sdmmc; + mmc1 = &emmc; + }; + chosen { stdout-path = "serial2:1500000n8"; }; @@ -25,7 +30,7 @@ compatible = "regulator-fixed"; gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0m1_gpio>; + pinctrl-0 = <&sdmmc0m1_pin>; regulator-name = "vcc_sd"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -73,44 +78,43 @@ leds { compatible = "gpio-leds"; - power { + power_led: led-0 { gpios = <&rk805 1 GPIO_ACTIVE_LOW>; linux,default-trigger = "mmc0"; }; - standby { + standby_led: led-1 { gpios = <&rk805 0 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; }; }; - sound { - compatible = "audio-graph-card"; - label = "rockchip,rk3328"; - dais = <&i2s1_p0 - &spdif_p0>; + spdif_sound: spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_dit>; + }; }; - spdif-dit { + spdif_dit: spdif-dit { compatible = "linux,spdif-dit"; #sound-dai-cells = <0>; - - port { - dit_p0_0: endpoint { - remote-endpoint = <&spdif_p0_0>; - }; - }; }; }; -&codec { +&analog_sound { status = "okay"; +}; - port@0 { - codec_p0_0: endpoint { - remote-endpoint = <&i2s1_p0_0>; - }; - }; +&codec { + mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; + status = "okay"; }; &cpu0 { @@ -162,6 +166,10 @@ status = "okay"; }; +&hdmi_sound { + status = "okay"; +}; + &hdmiphy { status = "okay"; }; @@ -169,7 +177,7 @@ &i2c1 { status = "okay"; - rk805: rk805@18 { + rk805: pmic@18 { compatible = "rockchip,rk805"; reg = <0x18>; interrupt-parent = <&gpio2>; @@ -277,16 +285,12 @@ }; }; -&i2s1 { +&i2s0 { status = "okay"; +}; - i2s1_p0: port { - i2s1_p0_0: endpoint { - dai-format = "i2s"; - mclk-fs = <256>; - remote-endpoint = <&codec_p0_0>; - }; - }; +&i2s1 { + status = "okay"; }; &io_domains { @@ -336,12 +340,6 @@ &spdif { pinctrl-0 = <&spdifm0_tx>; status = "okay"; - - spdif_p0: port { - spdif_p0_0: endpoint { - remote-endpoint = <&dit_p0_0>; - }; - }; }; &spi0 { @@ -383,6 +381,11 @@ status = "okay"; }; +&usbdrd3 { + dr_mode = "host"; + status = "okay"; +}; + &usb_host0_ehci { status = "okay"; }; Index: src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/sun50i-h6-r-ccu.h diff -u src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/sun50i-h6-r-ccu.h:1.1 src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/sun50i-h6-r-ccu.h:1.2 --- src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/sun50i-h6-r-ccu.h:1.1 Wed May 2 10:06:56 2018 +++ src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/sun50i-h6-r-ccu.h Sun Nov 7 16:57:39 2021 @@ -22,4 +22,6 @@ #define CLK_IR 11 #define CLK_W1 12 +#define CLK_R_APB2_RSB 13 + #endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */ Index: src/sys/external/gpl2/dts/dist/include/dt-bindings/input/linux-event-codes.h diff -u src/sys/external/gpl2/dts/dist/include/dt-bindings/input/linux-event-codes.h:1.9 src/sys/external/gpl2/dts/dist/include/dt-bindings/input/linux-event-codes.h:1.10 --- src/sys/external/gpl2/dts/dist/include/dt-bindings/input/linux-event-codes.h:1.9 Fri Jan 3 15:04:34 2020 +++ src/sys/external/gpl2/dts/dist/include/dt-bindings/input/linux-event-codes.h Sun Nov 7 16:57:39 2021 @@ -1,6 +1,6 @@ -/* $NetBSD: linux-event-codes.h,v 1.9 2020/01/03 15:04:34 skrll Exp $ */ +/* $NetBSD: linux-event-codes.h,v 1.10 2021/11/07 16:57:39 jmcneill Exp $ */ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ /* * Input event codes * @@ -517,6 +517,9 @@ #define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */ #define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */ #define KEY_IMAGES 0x1ba /* AL Image Browser */ +#define KEY_NOTIFICATION_CENTER 0x1bc /* Show/hide the notification center */ +#define KEY_PICKUP_PHONE 0x1bd /* Answer incoming call */ +#define KEY_HANGUP_PHONE 0x1be /* Decline incoming call */ #define KEY_DEL_EOL 0x1c0 #define KEY_DEL_EOS 0x1c1 @@ -544,6 +547,7 @@ #define KEY_FN_F 0x1e2 #define KEY_FN_S 0x1e3 #define KEY_FN_B 0x1e4 +#define KEY_FN_RIGHT_SHIFT 0x1e5 #define KEY_BRL_DOT1 0x1f1 #define KEY_BRL_DOT2 0x1f2 @@ -609,6 +613,7 @@ #define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */ #define KEY_ASSISTANT 0x247 /* AL Context-aware desktop assistant */ #define KEY_KBD_LAYOUT_NEXT 0x248 /* AC Next Keyboard Layout Select */ +#define KEY_EMOJI_PICKER 0x249 /* Show/hide emoji picker (HUTRR101) */ #define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ #define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ @@ -654,6 +659,9 @@ /* Electronic privacy screen control */ #define KEY_PRIVACY_SCREEN_TOGGLE 0x279 +/* Select an area of screen to be copied */ +#define KEY_SELECTIVE_SCREENSHOT 0x27a + /* * Some keyboards have keys which do not have a defined meaning, these keys * are intended to be programmed / bound to macros by the user. For most @@ -887,7 +895,8 @@ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ #define SW_PEN_INSERTED 0x0f /* set = pen inserted */ -#define SW_MAX 0x0f +#define SW_MACHINE_COVER 0x10 /* set = cover closed */ +#define SW_MAX 0x10 #define SW_CNT (SW_MAX+1) /* Index: src/sys/external/gpl2/dts/dist/include/dt-bindings/reset/sun50i-h6-r-ccu.h diff -u src/sys/external/gpl2/dts/dist/include/dt-bindings/reset/sun50i-h6-r-ccu.h:1.1 src/sys/external/gpl2/dts/dist/include/dt-bindings/reset/sun50i-h6-r-ccu.h:1.2 --- src/sys/external/gpl2/dts/dist/include/dt-bindings/reset/sun50i-h6-r-ccu.h:1.1 Wed May 2 10:06:56 2018 +++ src/sys/external/gpl2/dts/dist/include/dt-bindings/reset/sun50i-h6-r-ccu.h Sun Nov 7 16:57:39 2021 @@ -14,5 +14,6 @@ #define RST_R_APB2_I2C 4 #define RST_R_APB1_IR 5 #define RST_R_APB1_W1 6 +#define RST_R_APB2_RSB 7 #endif /* _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ */ Added files: Index: src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts diff -u /dev/null src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts:1.3 --- /dev/null Sun Nov 7 16:57:40 2021 +++ src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts Sun Nov 7 16:57:38 2021 @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS + * Author: Neil Armstrong <narmstr...@baylibre.com> + */ + +/dts-v1/; + +/* The Amlogic S922X Rev. C supports the same OPPs as the A311D variant */ +#include "meson-g12b-a311d.dtsi" +#include "meson-g12b-odroid-n2.dtsi" + +/ { + compatible = "hardkernel,odroid-n2-plus", "amlogic,s922x", "amlogic,g12b"; + model = "Hardkernel ODROID-N2Plus"; +}; + +&vddcpu_a { + regulator-min-microvolt = <680000>; + regulator-max-microvolt = <1040000>; + + pwms = <&pwm_ab 0 1500 0>; +}; + +&vddcpu_b { + regulator-min-microvolt = <680000>; + regulator-max-microvolt = <1040000>; + + pwms = <&pwm_AO_cd 1 1500 0>; +}; +