Module Name: src
Committed By: thorpej
Date: Wed Nov 24 02:01:15 UTC 2021
Modified Files:
src/lib/libc/arch/sh3: Makefile.inc
src/lib/libc/arch/sh3/sys: __sigtramp2.S
Added Files:
src/lib/libc/arch/sh3: genassym.cf
Log Message:
Decorate the SuperH signal trampoline with the appropriate .cfi
directives to allow exception unwind / backtrace across a signal
handler.
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/lib/libc/arch/sh3/Makefile.inc
cvs rdiff -u -r0 -r1.1 src/lib/libc/arch/sh3/genassym.cf
cvs rdiff -u -r1.4 -r1.5 src/lib/libc/arch/sh3/sys/__sigtramp2.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/arch/sh3/Makefile.inc
diff -u src/lib/libc/arch/sh3/Makefile.inc:1.8 src/lib/libc/arch/sh3/Makefile.inc:1.9
--- src/lib/libc/arch/sh3/Makefile.inc:1.8 Sun Oct 31 22:24:35 2021
+++ src/lib/libc/arch/sh3/Makefile.inc Wed Nov 24 02:01:15 2021
@@ -1,7 +1,9 @@
-# $NetBSD: Makefile.inc,v 1.8 2021/10/31 22:24:35 thorpej Exp $
+# $NetBSD: Makefile.inc,v 1.9 2021/11/24 02:01:15 thorpej Exp $
SRCS+= __sigtramp2.S
+CPPFLAGS+= -I.
+
.if ${MKSOFTFLOAT} != "no"
CPPFLAGS+= -DSOFTFLOAT # -DSOFTFLOAT_NEED_FIXUNS
Index: src/lib/libc/arch/sh3/sys/__sigtramp2.S
diff -u src/lib/libc/arch/sh3/sys/__sigtramp2.S:1.4 src/lib/libc/arch/sh3/sys/__sigtramp2.S:1.5
--- src/lib/libc/arch/sh3/sys/__sigtramp2.S:1.4 Thu Oct 15 05:50:15 2020
+++ src/lib/libc/arch/sh3/sys/__sigtramp2.S Wed Nov 24 02:01:15 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: __sigtramp2.S,v 1.4 2020/10/15 05:50:15 skrll Exp $ */
+/* $NetBSD: __sigtramp2.S,v 1.5 2021/11/24 02:01:15 thorpej Exp $ */
/*-
* Copyright (c) 2003 The NetBSD Foundation, Inc.
@@ -30,6 +30,7 @@
*/
#include "SYS.h"
+#include "assym.h"
/*
* The SH signal trampoline is invoked only to return from
@@ -44,11 +45,64 @@
* the top of the stack), because we want to avoid wasting two
* instructions to skip to the ucontext. Not that this order really
* matters, but I think this inconsistency deserves an explanation.
+ *
+ * The DWARF register numbers unforunately do not map directly to our
+ * _REG_* constants that are used to index the general registers in the
+ * ucontext_t at all.
+ *
+ * The stack pointer is, of course, r15, and there are several DWARF
+ * pseudo-registers to represent other bits of the context.
+ */
+
+#define DWARF_REG_PC 16
+#define DWARF_REG_PR 17
+#define DWARF_REG_GBR 18
+#define DWARF_REG_MACH 20
+#define DWARF_REG_MACL 21
+#define DWARF_REG_SR 22
+
+#define CFI_OFFSET_DWARF_REG(d, r) .cfi_offset d, r * 4
+
+ .text
+ .cfi_startproc simple
+ .cfi_signal_frame
+ .cfi_def_cfa 15, _UC_GREGS
+ CFI_OFFSET_DWARF_REG(0, _REG_R0)
+ CFI_OFFSET_DWARF_REG(1, _REG_R1)
+ CFI_OFFSET_DWARF_REG(2, _REG_R2)
+ CFI_OFFSET_DWARF_REG(3, _REG_R3)
+ CFI_OFFSET_DWARF_REG(4, _REG_R4)
+ CFI_OFFSET_DWARF_REG(5, _REG_R5)
+ CFI_OFFSET_DWARF_REG(6, _REG_R6)
+ CFI_OFFSET_DWARF_REG(7, _REG_R7)
+ CFI_OFFSET_DWARF_REG(9, _REG_R8)
+ CFI_OFFSET_DWARF_REG(9, _REG_R9)
+ CFI_OFFSET_DWARF_REG(10, _REG_R10)
+ CFI_OFFSET_DWARF_REG(11, _REG_R11)
+ CFI_OFFSET_DWARF_REG(12, _REG_R12)
+ CFI_OFFSET_DWARF_REG(13, _REG_R13)
+ CFI_OFFSET_DWARF_REG(14, _REG_R14)
+ CFI_OFFSET_DWARF_REG(15, _REG_R15)
+ CFI_OFFSET_DWARF_REG(DWARF_REG_PR, _REG_PR)
+ CFI_OFFSET_DWARF_REG(DWARF_REG_SR, _REG_SR)
+ CFI_OFFSET_DWARF_REG(DWARF_REG_GBR, _REG_GBR)
+ CFI_OFFSET_DWARF_REG(DWARF_REG_MACH, _REG_MACH)
+ CFI_OFFSET_DWARF_REG(DWARF_REG_MACL, _REG_MACL)
+ .cfi_return_column DWARF_REG_PC
+ CFI_OFFSET_DWARF_REG(DWARF_REG_PC, _REG_PC)
+
+/*
+ * The unwind entry includes one instruction slot prior to the trampoline
+ * because the unwinder will look up to (return PC - 1 insn) while unwinding.
+ * Normally this would be the jump / branch, but since there isn't one in
+ * this case, we place an explicit nop there instead.
*/
+ nop
+
NENTRY(__sigtramp_siginfo_2)
mov r15, r4 /* get pointer to ucontext */
SYSTRAP(setcontext) /* and call setcontext() */
mov r0, r4 /* exit with errno */
SYSTRAP(exit) /* if sigreturn fails */
-
+ .cfi_endproc
SET_ENTRY_SIZE(__sigtramp_siginfo_2)
Added files:
Index: src/lib/libc/arch/sh3/genassym.cf
diff -u /dev/null src/lib/libc/arch/sh3/genassym.cf:1.1
--- /dev/null Wed Nov 24 02:01:15 2021
+++ src/lib/libc/arch/sh3/genassym.cf Wed Nov 24 02:01:15 2021
@@ -0,0 +1,58 @@
+# $NetBSD: genassym.cf,v 1.1 2021/11/24 02:01:15 thorpej Exp $
+
+#
+# Copyright (c) 2021 The NetBSD Foundation, Inc.
+# All rights reserved.
+#
+# This code is derived from software contributed to The NetBSD Foundation
+# by Jason R. Thorpe.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+# ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+include <sys/types.h>
+include <ucontext.h>
+
+define _UC_GREGS offsetof(ucontext_t, uc_mcontext.__gregs[0])
+
+define _REG_R0 _REG_R0
+define _REG_R1 _REG_R1
+define _REG_R2 _REG_R2
+define _REG_R3 _REG_R3
+define _REG_R4 _REG_R4
+define _REG_R5 _REG_R5
+define _REG_R6 _REG_R6
+define _REG_R7 _REG_R7
+define _REG_R8 _REG_R8
+define _REG_R9 _REG_R9
+define _REG_R10 _REG_R10
+define _REG_R11 _REG_R11
+define _REG_R12 _REG_R12
+define _REG_R13 _REG_R13
+define _REG_R14 _REG_R14
+define _REG_R15 _REG_R15
+define _REG_GBR _REG_GBR
+define _REG_PC _REG_PC
+define _REG_SR _REG_SR
+define _REG_MACL _REG_MACL
+define _REG_MACH _REG_MACH
+define _REG_PR _REG_PR
