Module Name: src
Committed By: msaitoh
Date: Sun Dec 5 04:31:06 UTC 2021
Modified Files:
src/sys/arch/alpha/pci: ttwogareg.h
Log Message:
s/exchage/exchange/ in comment.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/alpha/pci/ttwogareg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/alpha/pci/ttwogareg.h
diff -u src/sys/arch/alpha/pci/ttwogareg.h:1.4 src/sys/arch/alpha/pci/ttwogareg.h:1.5
--- src/sys/arch/alpha/pci/ttwogareg.h:1.4 Mon Feb 6 02:14:15 2012
+++ src/sys/arch/alpha/pci/ttwogareg.h Sun Dec 5 04:31:06 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: ttwogareg.h,v 1.4 2012/02/06 02:14:15 matt Exp $ */
+/* $NetBSD: ttwogareg.h,v 1.5 2021/12/05 04:31:06 msaitoh Exp $ */
/*-
* Copyright (c) 1999 The NetBSD Foundation, Inc.
@@ -189,7 +189,7 @@ extern bus_addr_t ttwoga_gamma_cbus_bias
#define IOCSR_ENTLBEC 0x0000000000000080UL /* enable TLB error check */
#define IOCSR_ENCCMDA 0x0000000000000100UL /* enable CXACK check */
/* 0x0000000000000200UL must be zero */
-#define IOCSR_ENXXCHG 0x0000000000000400UL /* EV5 excl. exchage enable */
+#define IOCSR_ENXXCHG 0x0000000000000400UL /* EV5 excl. exchange enable */
/* 0x0000000000000800UL must be zero */
#define IOCSR_CAWWP0 0x0000000000001000UL /* CBUS c/a wr. wrong parity */
#define IOCSR_CAWWP2 0x0000000000002000UL /* CBUS c/a wr. wrong parity */
