Module Name: src
Committed By: msaitoh
Date: Thu Dec 9 14:33:19 UTC 2021
Modified Files:
src/sys/arch/x86/include: cacheinfo.h
Log Message:
Print TLB message consistently to improve readability.
Example:
cpu0: L2 cache: 256KB 64B/line 4-way
cpu0: L3 cache: 4MB 64B/line 16-way
cpu0: 64B prefetching
-cpu0: ITLB: 64 4KB entries 8-way, 2M/4M: 8 entries
+cpu0: ITLB: 64 4KB entries 8-way, 8 2M/4M entries
cpu0: DTLB: 64 4KB entries 4-way, 4 1GB entries 4-way
cpu0: L2 STLB: 1536 4KB entries 6-way
cpu0: Initial APIC ID 0
To generate a diff of this commit:
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/x86/include/cacheinfo.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
