Module Name: src
Committed By: riastradh
Date: Sun Dec 19 01:43:37 UTC 2021
Modified Files:
src/sys/external/bsd/drm2/dist/drm/i915: i915_irq.c intel_uncore.h
src/sys/external/bsd/drm2/dist/drm/i915/gt: intel_gt_irq.c
Log Message:
bus-spaceify raw_reg_read/write.
XXX heavily modified - maya
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys/external/bsd/drm2/dist/drm/i915/i915_irq.c
cvs rdiff -u -r1.2 -r1.3 \
src/sys/external/bsd/drm2/dist/drm/i915/intel_uncore.h
cvs rdiff -u -r1.2 -r1.3 \
src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_gt_irq.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/external/bsd/drm2/dist/drm/i915/i915_irq.c
diff -u src/sys/external/bsd/drm2/dist/drm/i915/i915_irq.c:1.20 src/sys/external/bsd/drm2/dist/drm/i915/i915_irq.c:1.21
--- src/sys/external/bsd/drm2/dist/drm/i915/i915_irq.c:1.20 Sat Dec 18 23:45:28 2021
+++ src/sys/external/bsd/drm2/dist/drm/i915/i915_irq.c Sun Dec 19 01:43:37 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: i915_irq.c,v 1.20 2021/12/18 23:45:28 riastradh Exp $ */
+/* $NetBSD: i915_irq.c,v 1.21 2021/12/19 01:43:37 riastradh Exp $ */
/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
*/
@@ -29,7 +29,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: i915_irq.c,v 1.20 2021/12/18 23:45:28 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: i915_irq.c,v 1.21 2021/12/19 01:43:37 riastradh Exp $");
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
@@ -2411,16 +2411,15 @@ static inline void gen8_master_intr_enab
static irqreturn_t gen8_irq_handler(int irq, void *arg)
{
struct drm_i915_private *dev_priv = arg;
- void __iomem * const regs = dev_priv->uncore.regs;
u32 master_ctl;
u32 gt_iir[4];
if (!intel_irqs_enabled(dev_priv))
return IRQ_NONE;
- master_ctl = gen8_master_intr_disable(regs);
+ master_ctl = gen8_master_intr_disable(&dev_priv->uncore);
if (!master_ctl) {
- gen8_master_intr_enable(regs);
+ gen8_master_intr_enable(&dev_priv->uncore);
return IRQ_NONE;
}
@@ -2434,7 +2433,7 @@ static irqreturn_t gen8_irq_handler(int
enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
}
- gen8_master_intr_enable(regs);
+ gen8_master_intr_enable(&dev_priv->uncore);
gen8_gt_irq_handler(&dev_priv->gt, master_ctl, gt_iir);
@@ -2444,15 +2443,14 @@ static irqreturn_t gen8_irq_handler(int
static u32
gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl)
{
- void __iomem * const regs = gt->uncore->regs;
u32 iir;
if (!(master_ctl & GEN11_GU_MISC_IRQ))
return 0;
- iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
+ iir = raw_reg_read(gt->uncore, GEN11_GU_MISC_IIR);
if (likely(iir))
- raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
+ raw_reg_write(gt->uncore, GEN11_GU_MISC_IIR, iir);
return iir;
}
@@ -2485,17 +2483,16 @@ static inline void gen11_master_intr_ena
static void
gen11_display_irq_handler(struct drm_i915_private *i915)
{
- void __iomem * const regs = i915->uncore.regs;
- const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
+ const u32 disp_ctl = raw_reg_read(&i915->uncore, GEN11_DISPLAY_INT_CTL);
disable_rpm_wakeref_asserts(&i915->runtime_pm);
/*
* GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
* for the display related bits.
*/
- raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0);
+ raw_reg_write(&i915->uncore, GEN11_DISPLAY_INT_CTL, 0x0);
gen8_de_irq_handler(i915, disp_ctl);
- raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,
+ raw_reg_write(&i915->uncore, GEN11_DISPLAY_INT_CTL,
GEN11_DISPLAY_IRQ_ENABLE);
enable_rpm_wakeref_asserts(&i915->runtime_pm);
@@ -2506,7 +2503,6 @@ __gen11_irq_handler(struct drm_i915_priv
u32 (*intr_disable)(void __iomem * const regs),
void (*intr_enable)(void __iomem * const regs))
{
- void __iomem * const regs = i915->uncore.regs;
struct intel_gt *gt = &i915->gt;
u32 master_ctl;
u32 gu_misc_iir;
@@ -2514,9 +2510,9 @@ __gen11_irq_handler(struct drm_i915_priv
if (!intel_irqs_enabled(i915))
return IRQ_NONE;
- master_ctl = intr_disable(regs);
+ master_ctl = intr_disable(&i915->uncore);
if (!master_ctl) {
- intr_enable(regs);
+ intr_enable(&i915->uncore);
return IRQ_NONE;
}
@@ -2529,7 +2525,7 @@ __gen11_irq_handler(struct drm_i915_priv
gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
- intr_enable(regs);
+ intr_enable(&i915->uncore);
gen11_gu_misc_irq_handler(gt, gu_misc_iir);
Index: src/sys/external/bsd/drm2/dist/drm/i915/intel_uncore.h
diff -u src/sys/external/bsd/drm2/dist/drm/i915/intel_uncore.h:1.2 src/sys/external/bsd/drm2/dist/drm/i915/intel_uncore.h:1.3
--- src/sys/external/bsd/drm2/dist/drm/i915/intel_uncore.h:1.2 Sat Dec 18 23:45:29 2021
+++ src/sys/external/bsd/drm2/dist/drm/i915/intel_uncore.h Sun Dec 19 01:43:37 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: intel_uncore.h,v 1.2 2021/12/18 23:45:29 riastradh Exp $ */
+/* $NetBSD: intel_uncore.h,v 1.3 2021/12/19 01:43:37 riastradh Exp $ */
/*
* Copyright © 2017 Intel Corporation
@@ -411,9 +411,18 @@ static inline int intel_uncore_write_and
return (reg_val & mask) != expected_val ? -EINVAL : 0;
}
+#ifdef __NetBSD__
+#define raw_reg_read(i915, reg) \
+ bus_space_read_4((i915)->regs_bst, (i915)->regs_bsh, \
+ i915_mmio_reg_offset(reg))
+#define raw_reg_write(i915, reg, value) \
+ bus_space_write_4((i915)->regs_bst, (i915)->regs_bsh, \
+ i915_mmio_reg_offset(reg), (value))
+#else
#define raw_reg_read(base, reg) \
readl(base + i915_mmio_reg_offset(reg))
#define raw_reg_write(base, reg, value) \
writel(value, base + i915_mmio_reg_offset(reg))
+#endif
#endif /* !__INTEL_UNCORE_H__ */
Index: src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_gt_irq.c
diff -u src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_gt_irq.c:1.2 src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_gt_irq.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_gt_irq.c:1.2 Sat Dec 18 23:45:30 2021
+++ src/sys/external/bsd/drm2/dist/drm/i915/gt/intel_gt_irq.c Sun Dec 19 01:43:37 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: intel_gt_irq.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $ */
+/* $NetBSD: intel_gt_irq.c,v 1.3 2021/12/19 01:43:37 riastradh Exp $ */
/*
* SPDX-License-Identifier: MIT
@@ -7,7 +7,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intel_gt_irq.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intel_gt_irq.c,v 1.3 2021/12/19 01:43:37 riastradh Exp $");
#include <linux/sched/clock.h>
@@ -45,13 +45,12 @@ static u32
gen11_gt_engine_identity(struct intel_gt *gt,
const unsigned int bank, const unsigned int bit)
{
- void __iomem * const regs = gt->uncore->regs;
u32 timeout_ts;
u32 ident;
lockdep_assert_held(>->irq_lock);
- raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
+ raw_reg_write(gt->uncore, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
/*
* NB: Specs do not specify how long to spin wait,
@@ -59,7 +58,7 @@ gen11_gt_engine_identity(struct intel_gt
*/
timeout_ts = (local_clock() >> 10) + 100;
do {
- ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank));
+ ident = raw_reg_read(gt->uncore, GEN11_INTR_IDENTITY_REG(bank));
} while (!(ident & GEN11_INTR_DATA_VALID) &&
!time_after32(local_clock() >> 10, timeout_ts));
@@ -69,7 +68,7 @@ gen11_gt_engine_identity(struct intel_gt
return 0;
}
- raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank),
+ raw_reg_write(gt->uncore, GEN11_INTR_IDENTITY_REG(bank),
GEN11_INTR_DATA_VALID);
return ident;
@@ -130,13 +129,12 @@ gen11_gt_identity_handler(struct intel_g
static void
gen11_gt_bank_handler(struct intel_gt *gt, const unsigned int bank)
{
- void __iomem * const regs = gt->uncore->regs;
unsigned long intr_dw;
unsigned int bit;
lockdep_assert_held(>->irq_lock);
- intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
+ intr_dw = raw_reg_read(gt->uncore, GEN11_GT_INTR_DW(bank));
for_each_set_bit(bit, &intr_dw, 32) {
const u32 ident = gen11_gt_engine_identity(gt, bank, bit);
@@ -145,7 +143,7 @@ gen11_gt_bank_handler(struct intel_gt *g
}
/* Clear must be after shared has been served for engine */
- raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw);
+ raw_reg_write(gt->uncore, GEN11_GT_INTR_DW(bank), intr_dw);
}
void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl)
@@ -165,12 +163,11 @@ void gen11_gt_irq_handler(struct intel_g
bool gen11_gt_reset_one_iir(struct intel_gt *gt,
const unsigned int bank, const unsigned int bit)
{
- void __iomem * const regs = gt->uncore->regs;
u32 dw;
lockdep_assert_held(>->irq_lock);
- dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
+ dw = raw_reg_read(gt->uncore, GEN11_GT_INTR_DW(bank));
if (dw & BIT(bit)) {
/*
* According to the BSpec, DW_IIR bits cannot be cleared without
@@ -184,7 +181,7 @@ bool gen11_gt_reset_one_iir(struct intel
* our bit, otherwise we are locking the register for
* everybody.
*/
- raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit));
+ raw_reg_write(gt->uncore, GEN11_GT_INTR_DW(bank), BIT(bit));
return true;
}
@@ -293,30 +290,29 @@ void gen6_gt_irq_handler(struct intel_gt
void gen8_gt_irq_ack(struct intel_gt *gt, u32 master_ctl, u32 gt_iir[4])
{
- void __iomem * const regs = gt->uncore->regs;
if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
- gt_iir[0] = raw_reg_read(regs, GEN8_GT_IIR(0));
+ gt_iir[0] = raw_reg_read(gt->uncore, GEN8_GT_IIR(0));
if (likely(gt_iir[0]))
- raw_reg_write(regs, GEN8_GT_IIR(0), gt_iir[0]);
+ raw_reg_write(gt->uncore, GEN8_GT_IIR(0), gt_iir[0]);
}
if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) {
- gt_iir[1] = raw_reg_read(regs, GEN8_GT_IIR(1));
+ gt_iir[1] = raw_reg_read(gt->uncore, GEN8_GT_IIR(1));
if (likely(gt_iir[1]))
- raw_reg_write(regs, GEN8_GT_IIR(1), gt_iir[1]);
+ raw_reg_write(gt->uncore, GEN8_GT_IIR(1), gt_iir[1]);
}
if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
- gt_iir[2] = raw_reg_read(regs, GEN8_GT_IIR(2));
+ gt_iir[2] = raw_reg_read(gt->uncore, GEN8_GT_IIR(2));
if (likely(gt_iir[2]))
- raw_reg_write(regs, GEN8_GT_IIR(2), gt_iir[2]);
+ raw_reg_write(gt->uncore, GEN8_GT_IIR(2), gt_iir[2]);
}
if (master_ctl & GEN8_GT_VECS_IRQ) {
- gt_iir[3] = raw_reg_read(regs, GEN8_GT_IIR(3));
+ gt_iir[3] = raw_reg_read(gt->uncore, GEN8_GT_IIR(3));
if (likely(gt_iir[3]))
- raw_reg_write(regs, GEN8_GT_IIR(3), gt_iir[3]);
+ raw_reg_write(gt->uncore, GEN8_GT_IIR(3), gt_iir[3]);
}
}
